Apollo Register Documentation  v2.4.2
CTIMER - Counter/Timer

CTIMER Register Index

  0x00000000:   TMR0 - Counter/Timer Register
  0x00000004:   CMPRA0 - Counter/Timer A0 Compare Registers
  0x00000008:   CMPRB0 - Counter/Timer B0 Compare Registers
  0x0000000C:   CTRL0 - Counter/Timer Control
  0x00000014:   CMPRAUXA0 - Counter/Timer A0 Compare Registers
  0x00000018:   CMPRAUXB0 - Counter/Timer B0 Compare Registers
  0x0000001C:   AUX0 - Counter/Timer Auxiliary
  0x00000020:   TMR1 - Counter/Timer Register
  0x00000024:   CMPRA1 - Counter/Timer A1 Compare Registers
  0x00000028:   CMPRB1 - Counter/Timer B1 Compare Registers
  0x0000002C:   CTRL1 - Counter/Timer Control
  0x00000034:   CMPRAUXA1 - Counter/Timer A1 Compare Registers
  0x00000038:   CMPRAUXB1 - Counter/Timer B1 Compare Registers
  0x0000003C:   AUX1 - Counter/Timer Auxiliary
  0x00000040:   TMR2 - Counter/Timer Register
  0x00000044:   CMPRA2 - Counter/Timer A2 Compare Registers
  0x00000048:   CMPRB2 - Counter/Timer B2 Compare Registers
  0x0000004C:   CTRL2 - Counter/Timer Control
  0x00000054:   CMPRAUXA2 - Counter/Timer A2 Compare Registers
  0x00000058:   CMPRAUXB2 - Counter/Timer B2 Compare Registers
  0x0000005C:   AUX2 - Counter/Timer Auxiliary
  0x00000060:   TMR3 - Counter/Timer Register
  0x00000064:   CMPRA3 - Counter/Timer A3 Compare Registers
  0x00000068:   CMPRB3 - Counter/Timer B3 Compare Registers
  0x0000006C:   CTRL3 - Counter/Timer Control
  0x00000074:   CMPRAUXA3 - Counter/Timer A3 Compare Registers
  0x00000078:   CMPRAUXB3 - Counter/Timer B3 Compare Registers
  0x0000007C:   AUX3 - Counter/Timer Auxiliary
  0x00000080:   TMR4 - Counter/Timer Register
  0x00000084:   CMPRA4 - Counter/Timer A4 Compare Registers
  0x00000088:   CMPRB4 - Counter/Timer B4 Compare Registers
  0x0000008C:   CTRL4 - Counter/Timer Control
  0x00000094:   CMPRAUXA4 - Counter/Timer A4 Compare Registers
  0x00000098:   CMPRAUXB4 - Counter/Timer B4 Compare Registers
  0x0000009C:   AUX4 - Counter/Timer Auxiliary
  0x000000A0:   TMR5 - Counter/Timer Register
  0x000000A4:   CMPRA5 - Counter/Timer A5 Compare Registers
  0x000000A8:   CMPRB5 - Counter/Timer B5 Compare Registers
  0x000000AC:   CTRL5 - Counter/Timer Control
  0x000000B4:   CMPRAUXA5 - Counter/Timer A5 Compare Registers
  0x000000B8:   CMPRAUXB5 - Counter/Timer B5 Compare Registers
  0x000000BC:   AUX5 - Counter/Timer Auxiliary
  0x000000C0:   TMR6 - Counter/Timer Register
  0x000000C4:   CMPRA6 - Counter/Timer A6 Compare Registers
  0x000000C8:   CMPRB6 - Counter/Timer B6 Compare Registers
  0x000000CC:   CTRL6 - Counter/Timer Control
  0x000000D4:   CMPRAUXA6 - Counter/Timer A6 Compare Registers
  0x000000D8:   CMPRAUXB6 - Counter/Timer B6 Compare Registers
  0x000000DC:   AUX6 - Counter/Timer Auxiliary
  0x000000E0:   TMR7 - Counter/Timer Register
  0x000000E4:   CMPRA7 - Counter/Timer A7 Compare Registers
  0x000000E8:   CMPRB7 - Counter/Timer B7 Compare Registers
  0x000000EC:   CTRL7 - Counter/Timer Control
  0x000000F4:   CMPRAUXA7 - Counter/Timer A7 Compare Registers
  0x000000F8:   CMPRAUXB7 - Counter/Timer B7 Compare Registers
  0x000000FC:   AUX7 - Counter/Timer Auxiliary
  0x00000100:   GLOBEN - Counter/Timer Global Enable
  0x00000104:   OUTCFG0 - Counter/Timer Output Config 0
  0x00000108:   OUTCFG1 - Counter/Timer Output Config 1
  0x0000010C:   OUTCFG2 - Counter/Timer Output Config 2
  0x00000114:   OUTCFG3 - Counter/Timer Output Config 3
  0x00000118:   INCFG - Counter/Timer Input Config
  0x00000140:   STCFG - Configuration Register
  0x00000144:   STTMR - System Timer Count Register (Real Time Counter)
  0x00000148:   CAPTURECONTROL - Capture Control Register
  0x00000150:   SCMPR0 - Compare Register A
  0x00000154:   SCMPR1 - Compare Register B
  0x00000158:   SCMPR2 - Compare Register C
  0x0000015C:   SCMPR3 - Compare Register D
  0x00000160:   SCMPR4 - Compare Register E
  0x00000164:   SCMPR5 - Compare Register F
  0x00000168:   SCMPR6 - Compare Register G
  0x0000016C:   SCMPR7 - Compare Register H
  0x000001E0:   SCAPT0 - Capture Register A
  0x000001E4:   SCAPT1 - Capture Register B
  0x000001E8:   SCAPT2 - Capture Register C
  0x000001EC:   SCAPT3 - Capture Register D
  0x000001F0:   SNVR0 - System Timer NVRAM_A Register
  0x000001F4:   SNVR1 - System Timer NVRAM_B Register
  0x000001F8:   SNVR2 - System Timer NVRAM_C Register
  0x000001FC:   SNVR3 - System Timer NVRAM_D Register
  0x00000200:   INTEN - Counter/Timer Interrupts: Enable
  0x00000204:   INTSTAT - Counter/Timer Interrupts: Status
  0x00000208:   INTCLR - Counter/Timer Interrupts: Clear
  0x0000020C:   INTSET - Counter/Timer Interrupts: Set
  0x00000300:   STMINTEN - STIMER Interrupt registers: Enable
  0x00000304:   STMINTSTAT - STIMER Interrupt registers: Status
  0x00000308:   STMINTCLR - STIMER Interrupt registers: Clear
  0x0000030C:   STMINTSET - STIMER Interrupt registers: Set

TMR0 - Counter/Timer Register

Address:

  Instance 0 Address:   0x40008000

Description:

This register holds the running time or event count for ctimer 0. This is either for each 16 bit half or for the whole 32 bit count when the pair is linked. If the pair is not linked, they can be running on seperate clocks and are completely independent.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTTMRB0
0x0
CTTMRA0
0x0

Bits Name RW Description
31:16 CTTMRB0 RO Counter/Timer B0.

15:0 CTTMRA0 RO Counter/Timer A0.


CMPRA0 - Counter/Timer A0 Compare Registers

Address:

  Instance 0 Address:   0x40008004

Description:

This contains the Compare limits for timer 0 A half.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1A0
0x0
CMPR0A0
0x0

Bits Name RW Description
31:16 CMPR1A0 RW Counter/Timer A0 Compare Register 1. Holds the upper limit for timer half A.

15:0 CMPR0A0 RW Counter/Timer A0 Compare Register 0. Holds the lower limit for timer half A.


CMPRB0 - Counter/Timer B0 Compare Registers

Address:

  Instance 0 Address:   0x40008008

Description:

This contains the Compare limits for timer 0 B half.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1B0
0x0
CMPR0B0
0x0

Bits Name RW Description
31:16 CMPR1B0 RW Counter/Timer B0 Compare Register 1. Holds the upper limit for timer half B.

15:0 CMPR0B0 RW Counter/Timer B0 Compare Register 0. Holds the lower limit for timer half B.


CTRL0 - Counter/Timer Control

Address:

  Instance 0 Address:   0x4000800C

Description:

This includes the Control bit fields for both halves of timer 0.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTLINK0
0x0
RSVD
0x0
TMRB0POL
0x0
TMRB0CLR
0x0
TMRB0IE1
0x0
TMRB0IE0
0x0
TMRB0FN
0x0
TMRB0CLK
0x0
TMRB0EN
0x0
RSVD
0x0
TMRA0POL
0x0
TMRA0CLR
0x0
TMRA0IE1
0x0
TMRA0IE0
0x0
TMRA0FN
0x0
TMRA0CLK
0x0
TMRA0EN
0x0

Bits Name RW Description
31 CTLINK0 RW Counter/Timer A0/B0 Link bit.

TWO_16BIT_TIMERS = 0x0 - Use A0/B0 timers as two independent 16-bit timers (default).
32BIT_TIMER = 0x1 - Link A0/B0 timers into a single 32-bit timer.
30:29 RSVD RO RESERVED

28 TMRB0POL RW Counter/Timer B0 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINB0 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINB0 pin is the inverse of the timer output.
27 TMRB0CLR RW Counter/Timer B0 Clear bit.

RUN = 0x0 - Allow counter/timer B0 to run
CLEAR = 0x1 - Holds counter/timer B0 at 0x0000.
26 TMRB0IE1 RW Counter/Timer B0 Interrupt Enable bit for COMPR1.

DIS = 0x0 - Disable counter/timer B0 from generating an interrupt based on COMPR1.
EN = 0x1 - Enable counter/timer B0 to generate an interrupt based on COMPR1.
25 TMRB0IE0 RW Counter/Timer B0 Interrupt Enable bit for COMPR0.

DIS = 0x0 - Disable counter/timer B0 from generating an interrupt based on COMPR0.
EN = 0x1 - Enable counter/timer B0 to generate an interrupt based on COMPR0
24:22 TMRB0FN RW Counter/Timer B0 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B0, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B0, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B0, assert, count to CMPR1B0, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B0, assert, count to CMPR1B0, deassert, restart.
SINGLEPATTERN = 0x4 - Single pattern.
REPEATPATTERN = 0x5 - Repeated pattern.
CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously.
ALTPWN = 0x7 - Alternate PWM
21:17 TMRB0CLK RW Counter/Timer B0 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINB.
HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4
HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV128 = 0x9 - Clock source is XT / 128
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)
XT_DIV4 = 0x10 - Clock source is XT / 4
XT_DIV8 = 0x11 - Clock source is XT / 8
XT_DIV32 = 0x12 - Clock source is XT / 32
RSVD = 0x13 - Clock source is Reserved.
CTMRA0 = 0x14 - Clock source is CTIMERA0 OUT.
CTMRB1 = 0x15 - Clock source is CTIMERB1 OUT.
CTMRA1 = 0x16 - Clock source is CTIMERA1 OUT.
CTMRA2 = 0x17 - Clock source is CTIMERA2 OUT.
CTMRB2 = 0x18 - Clock source is CTIMERB2 OUT.
CTMRB3 = 0x19 - Clock source is CTIMERB3 OUT.
CTMRB4 = 0x1A - Clock source is CTIMERB4 OUT.
CTMRB5 = 0x1B - Clock source is CTIMERB5 OUT.
CTMRB6 = 0x1C - Clock source is CTIMERB6 OUT.
BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses.
BUCKB = 0x1E - Clock source is Memory buck converter TON pulses.
BUCKA = 0x1F - Clock source is CPU buck converter TON pulses.
16 TMRB0EN RW Counter/Timer B0 Enable bit.

DIS = 0x0 - Counter/Timer B0 Disable.
EN = 0x1 - Counter/Timer B0 Enable.
15:13 RSVD RO RESERVED

12 TMRA0POL RW Counter/Timer A0 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINA0 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINA0 pin is the inverse of the timer output.
11 TMRA0CLR RW Counter/Timer A0 Clear bit.

RUN = 0x0 - Allow counter/timer A0 to run
CLEAR = 0x1 - Holds counter/timer A0 at 0x0000.
10 TMRA0IE1 RW Counter/Timer A0 Interrupt Enable bit based on COMPR1.

DIS = 0x0 - Disable counter/timer A0 from generating an interrupt based on COMPR1.
EN = 0x1 - Enable counter/timer A0 to generate an interrupt based on COMPR1.
9 TMRA0IE0 RW Counter/Timer A0 Interrupt Enable bit based on COMPR0.

DIS = 0x0 - Disable counter/timer A0 from generating an interrupt based on COMPR0.
EN = 0x1 - Enable counter/timer A0 to generate an interrupt based on COMPR0.
8:6 TMRA0FN RW Counter/Timer A0 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A0, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A0, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A0, assert, count to CMPR1A0, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A0, assert, count to CMPR1A0, deassert, restart.
SINGLEPATTERN = 0x4 - Single pattern.
REPEATPATTERN = 0x5 - Repeated pattern.
CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously.
ALTPWN = 0x7 - Alternate PWM
5:1 TMRA0CLK RW Counter/Timer A0 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINA.
HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4
HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV128 = 0x9 - Clock source is XT / 128
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)
XT_DIV4 = 0x10 - Clock source is XT / 4
XT_DIV8 = 0x11 - Clock source is XT / 8
XT_DIV32 = 0x12 - Clock source is XT / 32
RSVD = 0x13 - Clock source is Reserved.
CTMRB0 = 0x14 - Clock source is CTIMERB0 OUT.
CTMRA1 = 0x15 - Clock source is CTIMERA1 OUT.
CTMRB1 = 0x16 - Clock source is CTIMERB1 OUT.
CTMRA2 = 0x17 - Clock source is CTIMERA2 OUT.
CTMRB2 = 0x18 - Clock source is CTIMERB2 OUT.
CTMRB3 = 0x19 - Clock source is CTIMERB3 OUT.
CTMRB4 = 0x1A - Clock source is CTIMERB4 OUT.
CTMRB5 = 0x1B - Clock source is CTIMERB5 OUT.
CTMRB6 = 0x1C - Clock source is CTIMERB6 OUT.
BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses.
BUCKB = 0x1E - Clock source is Memory buck converter TON pulses.
BUCKA = 0x1F - Clock source is CPU buck converter TON pulses.
0 TMRA0EN RW Counter/Timer A0 Enable bit.

DIS = 0x0 - Counter/Timer A0 Disable.
EN = 0x1 - Counter/Timer A0 Enable.

CMPRAUXA0 - Counter/Timer A0 Compare Registers

Address:

  Instance 0 Address:   0x40008014

Description:

Enhanced compare limits for timer half A. This is valid if timer 0 is set to function 4 and function 5.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR3A0
0x0
CMPR2A0
0x0

Bits Name RW Description
31:16 CMPR3A0 RW Counter/Timer A0 Compare Register 3. Holds the upper limit for timer half A.

15:0 CMPR2A0 RW Counter/Timer A0 Compare Register 2. Holds the lower limit for timer half A.


CMPRAUXB0 - Counter/Timer B0 Compare Registers

Address:

  Instance 0 Address:   0x40008018

Description:

Enhanced compare limits for timer half B. This is valid if timer 0 is set to function 4 and function 5.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR3B0
0x0
CMPR2B0
0x0

Bits Name RW Description
31:16 CMPR3B0 RW Counter/Timer B0 Compare Register 3. Holds the upper limit for timer half B.

15:0 CMPR2B0 RW Counter/Timer B0 Compare Register 2. Holds the lower limit for timer half B.


AUX0 - Counter/Timer Auxiliary

Address:

  Instance 0 Address:   0x4000801C

Description:

Control bit fields for both halves of timer 0.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
TMRB0EN23
0x0
TMRB0POL23
0x0
TMRB0TINV
0x0
TMRB0NOSYNC
0x0
TMRB0TRIG
0x0
RSVD
0x0
TMRB0LMT
0x0
RSVD
0x0
TMRA0EN23
0x0
TMRA0POL23
0x0
TMRA0TINV
0x0
TMRA0NOSYNC
0x0
TMRA0TRIG
0x0
TMRA0LMT
0x0

Bits Name RW Description
31 RSVD RO RESERVED

30 TMRB0EN23 RW Counter/Timer B0 Upper compare enable.

DIS = 0x1 - Disable enhanced functions.
EN = 0x0 - Enable enhanced functions.
29 TMRB0POL23 RW Upper output polarity

NORM = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
28 TMRB0TINV RW Counter/Timer B0 Invert on trigger.

DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger
27 TMRB0NOSYNC RW Source clock synchronization control.

DIS = 0x0 - Synchronization on source clock
NOSYNC = 0x1 - No synchronization on source clock
26:23 TMRB0TRIG RW Counter/Timer B0 Trigger Select.

DIS = 0x0 - Trigger source is disabled.
A0OUT = 0x1 - Trigger source is CTIMERA0 OUT.
B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
A3OUT = 0x3 - Trigger source is CTIMERA3 OUT.
B2OUT = 0x4 - Trigger source is CTIMERB2 OUT.
B5OUT = 0x5 - Trigger source is CTIMERB5 OUT.
A4OUT = 0x6 - Trigger source is CTIMERA4 OUT.
B4OUT = 0x7 - Trigger source is CTIMERB4 OUT.
B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2.
A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2.
B7OUT2 = 0xA - Trigger source is CTIMERB7 OUT2.
A2OUT2 = 0xB - Trigger source is CTIMERA2 OUT2.
A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.
A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.
B5OUT2DUAL = 0xE - Trigger source is CTIMERB5 OUT2, dual edge.
A5OUT2DUAL = 0xF - Trigger source is CTIMERA5 OUT2, dual edge.
22 RSVD RO RESERVED

21:16 TMRB0LMT RW Counter/Timer B0 Pattern Limit Count.

15 RSVD RO RESERVED

14 TMRA0EN23 RW Counter/Timer A0 Upper compare enable.

DIS = 0x1 - Disable enhanced functions.
EN = 0x0 - Enable enhanced functions.
13 TMRA0POL23 RW Counter/Timer A0 Upper output polarity

NORM = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
12 TMRA0TINV RW Counter/Timer A0 Invert on trigger.

DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger
11 TMRA0NOSYNC RW Source clock synchronization control.

DIS = 0x0 - Synchronization on source clock
NOSYNC = 0x1 - No synchronization on source clock
10:7 TMRA0TRIG RW Counter/Timer A0 Trigger Select.

DIS = 0x0 - Trigger source is disabled.
B0OUT = 0x1 - Trigger source is CTIMERB0 OUT.
B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
A3OUT = 0x3 - Trigger source is CTIMERA3 OUT.
A1OUT = 0x4 - Trigger source is CTIMERA1 OUT.
B1OUT = 0x5 - Trigger source is CTIMERB1 OUT.
A5OUT = 0x6 - Trigger source is CTIMERA5 OUT.
B5OUT = 0x7 - Trigger source is CTIMERB5 OUT.
B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2.
A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2.
B6OUT2 = 0xA - Trigger source is CTIMERB6 OUT2.
A2OUT2 = 0xB - Trigger source is CTIMERA2 OUT2.
A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.
A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.
B4OUT2DUAL = 0xE - Trigger source is CTIMERB4 OUT2, dual edge.
A4OUT2DUAL = 0xF - Trigger source is CTIMERA4 OUT2, dual edge.
6:0 TMRA0LMT RW Counter/Timer A0 Pattern Limit Count.


TMR1 - Counter/Timer Register

Address:

  Instance 0 Address:   0x40008020

Description:

This register holds the running time or event count for ctimer 1. This is either for each 16 bit half or for the whole 32 bit count when the pair is linked. If the pair is not linked, they can be running on seperate clocks and are completely independent.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTTMRB1
0x0
CTTMRA1
0x0

Bits Name RW Description
31:16 CTTMRB1 RO Counter/Timer B1.

15:0 CTTMRA1 RO Counter/Timer A1.


CMPRA1 - Counter/Timer A1 Compare Registers

Address:

  Instance 0 Address:   0x40008024

Description:

This contains the Compare limits for timer 1 A half.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1A1
0x0
CMPR0A1
0x0

Bits Name RW Description
31:16 CMPR1A1 RW Counter/Timer A1 Compare Register 1.

15:0 CMPR0A1 RW Counter/Timer A1 Compare Register 0.


CMPRB1 - Counter/Timer B1 Compare Registers

Address:

  Instance 0 Address:   0x40008028

Description:

This contains the Compare limits for timer 1 B half.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1B1
0x0
CMPR0B1
0x0

Bits Name RW Description
31:16 CMPR1B1 RW Counter/Timer B1 Compare Register 1.

15:0 CMPR0B1 RW Counter/Timer B1 Compare Register 0.


CTRL1 - Counter/Timer Control

Address:

  Instance 0 Address:   0x4000802C

Description:

This includes the Control bit fields for both halves of timer 1.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTLINK1
0x0
RSVD
0x0
TMRB1POL
0x0
TMRB1CLR
0x0
TMRB1IE1
0x0
TMRB1IE0
0x0
TMRB1FN
0x0
TMRB1CLK
0x0
TMRB1EN
0x0
RSVD
0x0
TMRA1POL
0x0
TMRA1CLR
0x0
TMRA1IE1
0x0
TMRA1IE0
0x0
TMRA1FN
0x0
TMRA1CLK
0x0
TMRA1EN
0x0

Bits Name RW Description
31 CTLINK1 RW Counter/Timer A1/B1 Link bit.

TWO_16BIT_TIMERS = 0x0 - Use A1/B1 timers as two independent 16-bit timers (default).
32BIT_TIMER = 0x1 - Link A1/B1 timers into a single 32-bit timer.
30:29 RSVD RO RESERVED

28 TMRB1POL RW Counter/Timer B1 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINB1 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINB1 pin is the inverse of the timer output.
27 TMRB1CLR RW Counter/Timer B1 Clear bit.

RUN = 0x0 - Allow counter/timer B1 to run
CLEAR = 0x1 - Holds counter/timer B1 at 0x0000.
26 TMRB1IE1 RW Counter/Timer B1 Interrupt Enable bit for COMPR1.

DIS = 0x0 - Disable counter/timer B1 from generating an interrupt based on COMPR1.
EN = 0x1 - Enable counter/timer B1 to generate an interrupt based on COMPR1.
25 TMRB1IE0 RW Counter/Timer B1 Interrupt Enable bit for COMPR0.

DIS = 0x0 - Disable counter/timer B1 from generating an interrupt based on COMPR0.
EN = 0x1 - Enable counter/timer B1 to generate an interrupt based on COMPR0
24:22 TMRB1FN RW Counter/Timer B1 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B1, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B1, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B1, assert, count to CMPR1B1, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B1, assert, count to CMPR1B1, deassert, restart.
SINGLEPATTERN = 0x4 - Single pattern.
REPEATPATTERN = 0x5 - Repeated pattern.
CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously.
ALTPWN = 0x7 - Alternate PWM
21:17 TMRB1CLK RW Counter/Timer B1 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINB.
HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4
HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV128 = 0x9 - Clock source is XT / 128
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)
XT_DIV4 = 0x10 - Clock source is XT / 4
XT_DIV8 = 0x11 - Clock source is XT / 8
XT_DIV32 = 0x12 - Clock source is XT / 32
RSVD = 0x13 - Clock source is Reserved.
CTMRA1 = 0x14 - Clock source is CTIMERA1 OUT.
CTMRA0 = 0x15 - Clock source is CTIMERA0 OUT.
CTMRB0 = 0x16 - Clock source is CTIMERB0 OUT.
CTMRA2 = 0x17 - Clock source is CTIMERA2 OUT.
CTMRB2 = 0x18 - Clock source is CTIMERB2 OUT.
CTMRB3 = 0x19 - Clock source is CTIMERB3 OUT.
CTMRB4 = 0x1A - Clock source is CTIMERB4 OUT.
CTMRB5 = 0x1B - Clock source is CTIMERB5 OUT.
CTMRB6 = 0x1C - Clock source is CTIMERB6 OUT.
BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses.
BUCKB = 0x1E - Clock source is Memory buck converter TON pulses.
BUCKA = 0x1F - Clock source is CPU buck converter TON pulses.
16 TMRB1EN RW Counter/Timer B1 Enable bit.

DIS = 0x0 - Counter/Timer B1 Disable.
EN = 0x1 - Counter/Timer B1 Enable.
15:13 RSVD RO RESERVED

12 TMRA1POL RW Counter/Timer A1 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINA1 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINA1 pin is the inverse of the timer output.
11 TMRA1CLR RW Counter/Timer A1 Clear bit.

RUN = 0x0 - Allow counter/timer A1 to run
CLEAR = 0x1 - Holds counter/timer A1 at 0x0000.
10 TMRA1IE1 RW Counter/Timer A1 Interrupt Enable bit based on COMPR1.

DIS = 0x0 - Disable counter/timer A1 from generating an interrupt based on COMPR1.
EN = 0x1 - Enable counter/timer A1 to generate an interrupt based on COMPR1.
9 TMRA1IE0 RW Counter/Timer A1 Interrupt Enable bit based on COMPR0.

DIS = 0x0 - Disable counter/timer A1 from generating an interrupt based on COMPR0.
EN = 0x1 - Enable counter/timer A1 to generate an interrupt based on COMPR0.
8:6 TMRA1FN RW Counter/Timer A1 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A1, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A1, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A1, assert, count to CMPR1A1, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A1, assert, count to CMPR1A1, deassert, restart.
SINGLEPATTERN = 0x4 - Single pattern.
REPEATPATTERN = 0x5 - Repeated pattern.
CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously.
ALTPWN = 0x7 - Alternate PWM
TRIGCOPY = 0x7 - Replicate the trigger input
DUALTRIGPATTERN = 0x4 - Single pattern, trigger on either edge.
5:1 TMRA1CLK RW Counter/Timer A1 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINA.
HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4
HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV128 = 0x9 - Clock source is XT / 128
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)
XT_DIV4 = 0x10 - Clock source is XT / 4
XT_DIV8 = 0x11 - Clock source is XT / 8
XT_DIV32 = 0x12 - Clock source is XT / 32
RSVD = 0x13 - Clock source is Reserved.
CTMRB1 = 0x14 - Clock source is CTIMERB1 OUT.
CTMRA0 = 0x15 - Clock source is CTIMERA0 OUT.
CTMRB0 = 0x16 - Clock source is CTIMERB0 OUT.
CTMRA2 = 0x17 - Clock source is CTIMERA2 OUT.
CTMRB2 = 0x18 - Clock source is CTIMERB2 OUT.
CTMRB3 = 0x19 - Clock source is CTIMERB3 OUT.
CTMRB4 = 0x1A - Clock source is CTIMERB4 OUT.
CTMRB5 = 0x1B - Clock source is CTIMERB5 OUT.
CTMRB6 = 0x1C - Clock source is CTIMERB6 OUT.
BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses.
BUCKB = 0x1E - Clock source is Memory buck converter TON pulses.
BUCKA = 0x1F - Clock source is CPU buck converter TON pulses.
0 TMRA1EN RW Counter/Timer A1 Enable bit.

DIS = 0x0 - Counter/Timer A1 Disable.
EN = 0x1 - Counter/Timer A1 Enable.

CMPRAUXA1 - Counter/Timer A1 Compare Registers

Address:

  Instance 0 Address:   0x40008034

Description:

Enhanced compare limits for timer half A. This is valid if timer 1 is set to function 4 and function 5.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR3A1
0x0
CMPR2A1
0x0

Bits Name RW Description
31:16 CMPR3A1 RW Counter/Timer A1 Compare Register 3. Holds the upper limit for timer half A.

15:0 CMPR2A1 RW Counter/Timer A1 Compare Register 2. Holds the lower limit for timer half A.


CMPRAUXB1 - Counter/Timer B1 Compare Registers

Address:

  Instance 0 Address:   0x40008038

Description:

Enhanced compare limits for timer half B. This is valid if timer 1 is set to function 4 and function 5.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR3B1
0x0
CMPR2B1
0x0

Bits Name RW Description
31:16 CMPR3B1 RW Counter/Timer B1 Compare Register 3. Holds the upper limit for timer half B.

15:0 CMPR2B1 RW Counter/Timer B1 Compare Register 2. Holds the lower limit for timer half B.


AUX1 - Counter/Timer Auxiliary

Address:

  Instance 0 Address:   0x4000803C

Description:

Control bit fields for both halves of timer 0.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
TMRB1EN23
0x0
TMRB1POL23
0x0
TMRB1TINV
0x0
TMRB1NOSYNC
0x0
TMRB1TRIG
0x0
RSVD
0x0
TMRB1LMT
0x0
RSVD
0x0
TMRA1EN23
0x0
TMRA1POL23
0x0
TMRA1TINV
0x0
TMRA1NOSYNC
0x0
TMRA1TRIG
0x0
TMRA1LMT
0x0

Bits Name RW Description
31 RSVD RO RESERVED

30 TMRB1EN23 RW Counter/Timer B1 Upper compare enable.

DIS = 0x1 - Disable enhanced functions.
EN = 0x0 - Enable enhanced functions.
29 TMRB1POL23 RW Upper output polarity

NORM = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
28 TMRB1TINV RW Counter/Timer B1 Invert on trigger.

DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger
27 TMRB1NOSYNC RW Source clock synchronization control.

DIS = 0x0 - Synchronization on source clock
NOSYNC = 0x1 - No synchronization on source clock
26:23 TMRB1TRIG RW Counter/Timer B1 Trigger Select.

DIS = 0x0 - Trigger source is disabled.
A1OUT = 0x1 - Trigger source is CTIMERA1 OUT.
B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
A3OUT = 0x3 - Trigger source is CTIMERA3 OUT.
A6OUT = 0x4 - Trigger source is CTIMERA6 OUT.
B6OUT = 0x5 - Trigger source is CTIMERB6 OUT.
A0OUT = 0x6 - Trigger source is CTIMERA0 OUT.
B0OUT = 0x7 - Trigger source is CTIMERB0 OUT.
B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2.
A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2.
A4OUT2 = 0xA - Trigger source is CTIMERA4 OUT2.
B4OUT2 = 0xB - Trigger source is CTIMERB4 OUT2.
A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.
A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.
B5OUT2DUAL = 0xE - Trigger source is CTIMERB5 OUT2, dual edge.
A5OUT2DUAL = 0xF - Trigger source is CTIMERA5 OUT2, dual edge.
22 RSVD RO RESERVED

21:16 TMRB1LMT RW Counter/Timer B1 Pattern Limit Count.

15 RSVD RO RESERVED

14 TMRA1EN23 RW Counter/Timer A1 Upper compare enable.

DIS = 0x1 - Disable enhanced functions.
EN = 0x0 - Enable enhanced functions.
13 TMRA1POL23 RW Counter/Timer A1 Upper output polarity

NORMAL = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
12 TMRA1TINV RW Counter/Timer A1 Invert on trigger.

DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger
11 TMRA1NOSYNC RW Source clock synchronization control.

DIS = 0x0 - Synchronization on source clock
NOSYNC = 0x1 - No synchronization on source clock
10:7 TMRA1TRIG RW Counter/Timer A1 Trigger Select.

DIS = 0x0 - Trigger source is disabled.
B1OUT = 0x1 - Trigger source is CTIMERB1 OUT.
B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
A3OUT = 0x3 - Trigger source is CTIMERA3 OUT.
A0OUT = 0x4 - Trigger source is CTIMERA0 OUT.
B0OUT = 0x5 - Trigger source is CTIMERB0 OUT.
A5OUT = 0x6 - Trigger source is CTIMERA5 OUT.
B5OUT = 0x7 - Trigger source is CTIMERB5 OUT.
B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2.
A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2.
A4OUT2 = 0xA - Trigger source is CTIMERA4 OUT2.
B4OUT2 = 0xB - Trigger source is CTIMERB4 OUT2.
A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.
A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.
B5OUT2DUAL = 0xE - Trigger source is CTIMERB5 OUT2, dual edge.
A5OUT2DUAL = 0xF - Trigger source is CTIMERA5 OUT2, dual edge.
6:0 TMRA1LMT RW Counter/Timer A1 Pattern Limit Count.


TMR2 - Counter/Timer Register

Address:

  Instance 0 Address:   0x40008040

Description:

This register holds the running time or event count for ctimer 2. This is either for each 16 bit half or for the whole 32 bit count when the pair is linked. If the pair is not linked, they can be running on seperate clocks and are completely independent.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTTMRB2
0x0
CTTMRA2
0x0

Bits Name RW Description
31:16 CTTMRB2 RO Counter/Timer B2.

15:0 CTTMRA2 RO Counter/Timer A2.


CMPRA2 - Counter/Timer A2 Compare Registers

Address:

  Instance 0 Address:   0x40008044

Description:

This register holds the compare limits for timer 2 A half.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1A2
0x0
CMPR0A2
0x0

Bits Name RW Description
31:16 CMPR1A2 RW Counter/Timer A2 Compare Register 1.

15:0 CMPR0A2 RW Counter/Timer A2 Compare Register 0.


CMPRB2 - Counter/Timer B2 Compare Registers

Address:

  Instance 0 Address:   0x40008048

Description:

This register holds the compare limits for timer 2 B half.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1B2
0x0
CMPR0B2
0x0

Bits Name RW Description
31:16 CMPR1B2 RW Counter/Timer B2 Compare Register 1.

15:0 CMPR0B2 RW Counter/Timer B2 Compare Register 0.


CTRL2 - Counter/Timer Control

Address:

  Instance 0 Address:   0x4000804C

Description:

This register holds the control bit fields for both halves of timer 2.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTLINK2
0x0
RSVD
0x0
TMRB2POL
0x0
TMRB2CLR
0x0
TMRB2IE1
0x0
TMRB2IE0
0x0
TMRB2FN
0x0
TMRB2CLK
0x0
TMRB2EN
0x0
RSVD
0x0
TMRA2POL
0x0
TMRA2CLR
0x0
TMRA2IE1
0x0
TMRA2IE0
0x0
TMRA2FN
0x0
TMRA2CLK
0x0
TMRA2EN
0x0

Bits Name RW Description
31 CTLINK2 RW Counter/Timer A2/B2 Link bit.

TWO_16BIT_TIMERS = 0x0 - Use A2/B2 timers as two independent 16-bit timers (default).
32BIT_TIMER = 0x1 - Link A2/B2 timers into a single 32-bit timer.
30:29 RSVD RO RESERVED

28 TMRB2POL RW Counter/Timer B2 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINB2 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINB2 pin is the inverse of the timer output.
27 TMRB2CLR RW Counter/Timer B2 Clear bit.

RUN = 0x0 - Allow counter/timer B2 to run
CLEAR = 0x1 - Holds counter/timer B2 at 0x0000.
26 TMRB2IE1 RW Counter/Timer B2 Interrupt Enable bit for COMPR1.

DIS = 0x0 - Disable counter/timer B2 from generating an interrupt based on COMPR1.
EN = 0x1 - Enable counter/timer B2 to generate an interrupt based on COMPR1.
25 TMRB2IE0 RW Counter/Timer B2 Interrupt Enable bit for COMPR0.

DIS = 0x0 - Disable counter/timer B2 from generating an interrupt based on COMPR0.
EN = 0x1 - Enable counter/timer B2 to generate an interrupt based on COMPR0
24:22 TMRB2FN RW Counter/Timer B2 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B2, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B2, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B2, assert, count to CMPR1B2, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B2, assert, count to CMPR1B2, deassert, restart.
SINGLEPATTERN = 0x4 - Single pattern.
REPEATPATTERN = 0x5 - Repeated pattern.
CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously.
ALTPWN = 0x7 - Alternate PWM
21:17 TMRB2CLK RW Counter/Timer B2 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINB.
HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4
HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV128 = 0x9 - Clock source is XT / 128
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)
XT_DIV4 = 0x10 - Clock source is XT / 4
XT_DIV8 = 0x11 - Clock source is XT / 8
XT_DIV32 = 0x12 - Clock source is XT / 32
RSVD = 0x13 - Clock source is Reserved.
CTMRA2 = 0x14 - Clock source is CTIMERA2 OUT.
CTMRB3 = 0x15 - Clock source is CTIMERA3 OUT.
CTMRA3 = 0x16 - Clock source is CTIMERB3 OUT.
CTMRA4 = 0x17 - Clock source is CTIMERA4 OUT.
CTMRB4 = 0x18 - Clock source is CTIMERB4 OUT.
CTMRB0 = 0x19 - Clock source is CTIMERB0 OUT.
CTMRB1 = 0x1A - Clock source is CTIMERB1 OUT.
CTMRB5 = 0x1B - Clock source is CTIMERB5 OUT.
CTMRB6 = 0x1C - Clock source is CTIMERB6 OUT.
BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses.
BUCKB = 0x1E - Clock source is Memory buck converter TON pulses.
BUCKA = 0x1F - Clock source is CPU buck converter TON pulses.
16 TMRB2EN RW Counter/Timer B2 Enable bit.

DIS = 0x0 - Counter/Timer B2 Disable.
EN = 0x1 - Counter/Timer B2 Enable.
15:13 RSVD RO RESERVED

12 TMRA2POL RW Counter/Timer A2 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINA2 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINA2 pin is the inverse of the timer output.
11 TMRA2CLR RW Counter/Timer A2 Clear bit.

RUN = 0x0 - Allow counter/timer A2 to run
CLEAR = 0x1 - Holds counter/timer A2 at 0x0000.
10 TMRA2IE1 RW Counter/Timer A2 Interrupt Enable bit based on COMPR1.

DIS = 0x0 - Disable counter/timer A2 from generating an interrupt based on COMPR1.
EN = 0x1 - Enable counter/timer A2 to generate an interrupt based on COMPR1.
9 TMRA2IE0 RW Counter/Timer A2 Interrupt Enable bit based on COMPR0.

DIS = 0x0 - Disable counter/timer A2 from generating an interrupt based on COMPR0.
EN = 0x1 - Enable counter/timer A2 to generate an interrupt based on COMPR0.
8:6 TMRA2FN RW Counter/Timer A2 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A2, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A2, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A2, assert, count to CMPR1A2, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A2, assert, count to CMPR1A2, deassert, restart.
SINGLEPATTERN = 0x4 - Single pattern.
REPEATPATTERN = 0x5 - Repeated pattern.
CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously.
ALTPWN = 0x7 - Alternate PWM
5:1 TMRA2CLK RW Counter/Timer A2 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINA.
HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4
HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV128 = 0x9 - Clock source is XT / 128
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)
XT_DIV4 = 0x10 - Clock source is XT / 4
XT_DIV8 = 0x11 - Clock source is XT / 8
XT_DIV32 = 0x12 - Clock source is XT / 32
RSVD = 0x13 - Clock source is Reserved.
CTMRB2 = 0x14 - Clock source is CTIMERB2 OUT.
CTMRB3 = 0x15 - Clock source is CTIMERA3 OUT.
CTMRA3 = 0x16 - Clock source is CTIMERB3 OUT.
CTMRA4 = 0x17 - Clock source is CTIMERA4 OUT.
CTMRB4 = 0x18 - Clock source is CTIMERB4 OUT.
CTMRB0 = 0x19 - Clock source is CTIMERB0 OUT.
CTMRB1 = 0x1A - Clock source is CTIMERB1 OUT.
CTMRB5 = 0x1B - Clock source is CTIMERB5 OUT.
CTMRB6 = 0x1C - Clock source is CTIMERB6 OUT.
BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses.
BUCKB = 0x1E - Clock source is Memory buck converter TON pulses.
BUCKA = 0x1F - Clock source is CPU buck converter TON pulses.
0 TMRA2EN RW Counter/Timer A2 Enable bit.

DIS = 0x0 - Counter/Timer A2 Disable.
EN = 0x1 - Counter/Timer A2 Enable.

CMPRAUXA2 - Counter/Timer A2 Compare Registers

Address:

  Instance 0 Address:   0x40008054

Description:

Enhanced compare limits for timer half A.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR3A2
0x0
CMPR2A2
0x0

Bits Name RW Description
31:16 CMPR3A2 RW Counter/Timer A2 Compare Register 3. Holds the upper limit for timer half A.

15:0 CMPR2A2 RW Counter/Timer A2 Compare Register 2. Holds the lower limit for timer half A.


CMPRAUXB2 - Counter/Timer B2 Compare Registers

Address:

  Instance 0 Address:   0x40008058

Description:

Enhanced compare limits for timer half B.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR3B2
0x0
CMPR2B2
0x0

Bits Name RW Description
31:16 CMPR3B2 RW Counter/Timer B2 Compare Register 3. Holds the upper limit for timer half B.

15:0 CMPR2B2 RW Counter/Timer B2 Compare Register 2. Holds the lower limit for timer half B.


AUX2 - Counter/Timer Auxiliary

Address:

  Instance 0 Address:   0x4000805C

Description:

Control bit fields for both halves of timer 0.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
TMRB2EN23
0x0
TMRB2POL23
0x0
TMRB2TINV
0x0
TMRB2NOSYNC
0x0
TMRB2TRIG
0x0
RSVD
0x0
TMRB2LMT
0x0
RSVD
0x0
TMRA2EN23
0x0
TMRA2POL23
0x0
TMRA2TINV
0x0
TMRA2NOSYNC
0x0
TMRA2TRIG
0x0
TMRA2LMT
0x0

Bits Name RW Description
31 RSVD RO RESERVED

30 TMRB2EN23 RW Counter/Timer B2 Upper compare enable.

DIS = 0x1 - Disable enhanced functions.
EN = 0x0 - Enable enhanced functions.
29 TMRB2POL23 RW Upper output polarity

NORM = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
28 TMRB2TINV RW Counter/Timer B2 Invert on trigger.

DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger
27 TMRB2NOSYNC RW Source clock synchronization control.

DIS = 0x0 - Synchronization on source clock
NOSYNC = 0x1 - No synchronization on source clock
26:23 TMRB2TRIG RW Counter/Timer B2 Trigger Select.

DIS = 0x0 - Trigger source is disabled.
A2OUT = 0x1 - Trigger source is CTIMERA2 OUT.
B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
A3OUT = 0x3 - Trigger source is CTIMERA3 OUT.
A1OUT = 0x4 - Trigger source is CTIMERA1 OUT.
B1OUT = 0x5 - Trigger source is CTIMERB1 OUT.
A4OUT = 0x6 - Trigger source is CTIMERA4 OUT.
B4OUT = 0x7 - Trigger source is CTIMERB4 OUT.
B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2.
A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2.
A5OUT2 = 0xA - Trigger source is CTIMERA5 OUT2.
B5OUT2 = 0xB - Trigger source is CTIMERB5 OUT2.
A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.
A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.
B4OUT2DUAL = 0xE - Trigger source is CTIMERB4 OUT2, dual edge.
A4OUT2DUAL = 0xF - Trigger source is CTIMERA4 OUT2, dual edge.
22 RSVD RO RESERVED

21:16 TMRB2LMT RW Counter/Timer B2 Pattern Limit Count.

15 RSVD RO RESERVED

14 TMRA2EN23 RW Counter/Timer A2 Upper compare enable.

DIS = 0x1 - Disable enhanced functions.
EN = 0x0 - Enable enhanced functions.
13 TMRA2POL23 RW Counter/Timer A2 Upper output polarity

NORM = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
12 TMRA2TINV RW Counter/Timer A2 Invert on trigger.

DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger
11 TMRA2NOSYNC RW Source clock synchronization control.

DIS = 0x0 - Synchronization on source clock
NOSYNC = 0x1 - No synchronization on source clock
10:7 TMRA2TRIG RW Counter/Timer A2 Trigger Select.

DIS = 0x0 - Trigger source is disabled.
B2OUT = 0x1 - Trigger source is CTIMERB2 OUT.
B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
A3OUT = 0x3 - Trigger source is CTIMERA3 OUT.
A0OUT = 0x4 - Trigger source is CTIMERA0 OUT.
B0OUT = 0x5 - Trigger source is CTIMERB0 OUT.
A4OUT = 0x6 - Trigger source is CTIMERA4 OUT.
B4OUT = 0x7 - Trigger source is CTIMERB4 OUT.
B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2.
A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2.
A5OUT2 = 0xA - Trigger source is CTIMERA5 OUT2.
B5OUT2 = 0xB - Trigger source is CTIMERB5 OUT2.
A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.
A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.
B4OUT2DUAL = 0xE - Trigger source is CTIMERB4 OUT2, dual edge.
A4OUT2DUAL = 0xF - Trigger source is CTIMERA4 OUT2, dual edge.
6:0 TMRA2LMT RW Counter/Timer A2 Pattern Limit Count.


TMR3 - Counter/Timer Register

Address:

  Instance 0 Address:   0x40008060

Description:

Counter/Timer Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTTMRB3
0x0
CTTMRA3
0x0

Bits Name RW Description
31:16 CTTMRB3 RO Counter/Timer B3.

15:0 CTTMRA3 RO Counter/Timer A3.


CMPRA3 - Counter/Timer A3 Compare Registers

Address:

  Instance 0 Address:   0x40008064

Description:

This register holds the compare limits for timer half A.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1A3
0x0
CMPR0A3
0x0

Bits Name RW Description
31:16 CMPR1A3 RW Counter/Timer A3 Compare Register 1.

15:0 CMPR0A3 RW Counter/Timer A3 Compare Register 0.


CMPRB3 - Counter/Timer B3 Compare Registers

Address:

  Instance 0 Address:   0x40008068

Description:

This register holds the compare limits for timer half B.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1B3
0x0
CMPR0B3
0x0

Bits Name RW Description
31:16 CMPR1B3 RW Counter/Timer B3 Compare Register 1.

15:0 CMPR0B3 RW Counter/Timer B3 Compare Register 0.


CTRL3 - Counter/Timer Control

Address:

  Instance 0 Address:   0x4000806C

Description:

This register holds the control bit fields for both halves of timer 3.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTLINK3
0x0
RSVD
0x0
TMRB3POL
0x0
TMRB3CLR
0x0
TMRB3IE1
0x0
TMRB3IE0
0x0
TMRB3FN
0x0
TMRB3CLK
0x0
TMRB3EN
0x0
ADCEN
0x0
RSVD
0x0
TMRA3POL
0x0
TMRA3CLR
0x0
TMRA3IE1
0x0
TMRA3IE0
0x0
TMRA3FN
0x0
TMRA3CLK
0x0
TMRA3EN
0x0

Bits Name RW Description
31 CTLINK3 RW Counter/Timer A3/B3 Link bit.

TWO_16BIT_TIMERS = 0x0 - Use A3/B3 timers as two independent 16-bit timers (default).
32BIT_TIMER = 0x1 - Link A3/B3 timers into a single 32-bit timer.
30:29 RSVD RO RESERVED

28 TMRB3POL RW Counter/Timer B3 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINB3 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINB3 pin is the inverse of the timer output.
27 TMRB3CLR RW Counter/Timer B3 Clear bit.

RUN = 0x0 - Allow counter/timer B3 to run
CLEAR = 0x1 - Holds counter/timer B3 at 0x0000.
26 TMRB3IE1 RW Counter/Timer B3 Interrupt Enable bit for COMPR1.

DIS = 0x0 - Disable counter/timer B3 from generating an interrupt based on COMPR1.
EN = 0x1 - Enable counter/timer B3 to generate an interrupt based on COMPR1.
25 TMRB3IE0 RW Counter/Timer B3 Interrupt Enable bit for COMPR0.

DIS = 0x0 - Disable counter/timer B3 from generating an interrupt based on COMPR0.
EN = 0x1 - Enable counter/timer B3 to generate an interrupt based on COMPR0
24:22 TMRB3FN RW Counter/Timer B3 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B3, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B3, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B3, assert, count to CMPR1B3, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B3, assert, count to CMPR1B3, deassert, restart.
SINGLEPATTERN = 0x4 - Single pattern.
REPEATPATTERN = 0x5 - Repeated pattern.
CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously.
ALTPWN = 0x7 - Alternate PWM
21:17 TMRB3CLK RW Counter/Timer B3 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINB.
HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4
HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV128 = 0x9 - Clock source is XT / 128
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)
XT_DIV4 = 0x10 - Clock source is XT / 4
XT_DIV8 = 0x11 - Clock source is XT / 8
XT_DIV32 = 0x12 - Clock source is XT / 32
RSVD = 0x13 - Clock source is Reserved.
CTMRA3 = 0x14 - Clock source is CTIMERA3 OUT.
CTMRA2 = 0x15 - Clock source is CTIMERA2 OUT.
CTMRB2 = 0x16 - Clock source is CTIMERB2 OUT.
CTMRA4 = 0x17 - Clock source is CTIMERA4 OUT.
CTMRB4 = 0x18 - Clock source is CTIMERB4 OUT.
CTMRB0 = 0x19 - Clock source is CTIMERB0 OUT.
CTMRB1 = 0x1A - Clock source is CTIMERB1 OUT.
CTMRB5 = 0x1B - Clock source is CTIMERB5 OUT.
CTMRB6 = 0x1C - Clock source is CTIMERB6 OUT.
BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses.
BUCKB = 0x1E - Clock source is Memory buck converter TON pulses.
BUCKA = 0x1F - Clock source is CPU buck converter TON pulses.
16 TMRB3EN RW Counter/Timer B3 Enable bit.

DIS = 0x0 - Counter/Timer B3 Disable.
EN = 0x1 - Counter/Timer B3 Enable.
15 ADCEN RW Special Timer A3 enable for ADC function.

14:13 RSVD RO RESERVED

12 TMRA3POL RW Counter/Timer A3 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINA3 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINA3 pin is the inverse of the timer output.
11 TMRA3CLR RW Counter/Timer A3 Clear bit.

RUN = 0x0 - Allow counter/timer A3 to run
CLEAR = 0x1 - Holds counter/timer A3 at 0x0000.
10 TMRA3IE1 RW Counter/Timer A3 Interrupt Enable bit based on COMPR1.

DIS = 0x0 - Disable counter/timer A3 from generating an interrupt based on COMPR1.
EN = 0x1 - Enable counter/timer A3 to generate an interrupt based on COMPR1.
9 TMRA3IE0 RW Counter/Timer A3 Interrupt Enable bit based on COMPR0.

DIS = 0x0 - Disable counter/timer A3 from generating an interrupt based on COMPR0.
EN = 0x1 - Enable counter/timer A3 to generate an interrupt based on COMPR0.
8:6 TMRA3FN RW Counter/Timer A3 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A3, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A3, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A3, assert, count to CMPR1A3, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A3, assert, count to CMPR1A3, deassert, restart.
SINGLEPATTERN = 0x4 - Single pattern.
REPEATPATTERN = 0x5 - Repeated pattern.
CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously.
ALTPWN = 0x7 - Alternate PWM
5:1 TMRA3CLK RW Counter/Timer A3 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINA.
HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4
HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV128 = 0x9 - Clock source is XT / 128
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)
XT_DIV4 = 0x10 - Clock source is XT / 4
XT_DIV8 = 0x11 - Clock source is XT / 8
XT_DIV32 = 0x12 - Clock source is XT / 32
RSVD = 0x13 - Clock source is Reserved.
CTMRB3 = 0x14 - Clock source is CTIMERB3 OUT.
CTMRA2 = 0x15 - Clock source is CTIMERA2 OUT.
CTMRB2 = 0x16 - Clock source is CTIMERB2 OUT.
CTMRA4 = 0x17 - Clock source is CTIMERA4 OUT.
CTMRB4 = 0x18 - Clock source is CTIMERB4 OUT.
CTMRB0 = 0x19 - Clock source is CTIMERB0 OUT.
CTMRB1 = 0x1A - Clock source is CTIMERB1 OUT.
CTMRB5 = 0x1B - Clock source is CTIMERB5 OUT.
CTMRB6 = 0x1C - Clock source is CTIMERB6 OUT.
BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses.
BUCKB = 0x1E - Clock source is Memory buck converter TON pulses.
BUCKA = 0x1F - Clock source is CPU buck converter TON pulses.
0 TMRA3EN RW Counter/Timer A3 Enable bit.

DIS = 0x0 - Counter/Timer A3 Disable.
EN = 0x1 - Counter/Timer A3 Enable.

CMPRAUXA3 - Counter/Timer A3 Compare Registers

Address:

  Instance 0 Address:   0x40008074

Description:

Enhanced compare limits for timer half A.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR3A3
0x0
CMPR2A3
0x0

Bits Name RW Description
31:16 CMPR3A3 RW Counter/Timer A3 Compare Register 3. Holds the upper limit for timer half A.

15:0 CMPR2A3 RW Counter/Timer A3 Compare Register 2. Holds the lower limit for timer half A.


CMPRAUXB3 - Counter/Timer B3 Compare Registers

Address:

  Instance 0 Address:   0x40008078

Description:

Enhanced compare limits for timer half B.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR3B3
0x0
CMPR2B3
0x0

Bits Name RW Description
31:16 CMPR3B3 RW Counter/Timer B3 Compare Register 3. Holds the upper limit for timer half B.

15:0 CMPR2B3 RW Counter/Timer B3 Compare Register 2. Holds the lower limit for timer half B.


AUX3 - Counter/Timer Auxiliary

Address:

  Instance 0 Address:   0x4000807C

Description:

Control bit fields for both halves of timer 0.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
TMRB3EN23
0x0
TMRB3POL23
0x0
TMRB3TINV
0x0
TMRB3NOSYNC
0x0
TMRB3TRIG
0x0
RSVD
0x0
TMRB3LMT
0x0
RSVD
0x0
TMRA3EN23
0x0
TMRA3POL23
0x0
TMRA3TINV
0x0
TMRA3NOSYNC
0x0
TMRA3TRIG
0x0
TMRA3LMT
0x0

Bits Name RW Description
31 RSVD RO RESERVED

30 TMRB3EN23 RW Counter/Timer B3 Upper compare enable.

DIS = 0x1 - Disable enhanced functions.
EN = 0x0 - Enable enhanced functions.
29 TMRB3POL23 RW Upper output polarity

NORM = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
28 TMRB3TINV RW Counter/Timer B3 Invert on trigger.

DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger
27 TMRB3NOSYNC RW Source clock synchronization control.

DIS = 0x0 - Synchronization on source clock
NOSYNC = 0x1 - No synchronization on source clock
26:23 TMRB3TRIG RW Counter/Timer B3 Trigger Select.

DIS = 0x0 - Trigger source is disabled.
A3OUT = 0x1 - Trigger source is CTIMERA3 OUT.
B2OUT = 0x2 - Trigger source is CTIMERB2 OUT.
A2OUT = 0x3 - Trigger source is CTIMERA2 OUT.
A4OUT = 0x4 - Trigger source is CTIMERA4 OUT.
B4OUT = 0x5 - Trigger source is CTIMERB4 OUT.
A6OUT = 0x6 - Trigger source is CTIMERA6 OUT.
B6OUT = 0x7 - Trigger source is CTIMERB6 OUT.
B5OUT2 = 0x8 - Trigger source is CTIMERB5 OUT2.
A5OUT2 = 0x9 - Trigger source is CTIMERA5 OUT2.
A1OUT2 = 0xA - Trigger source is CTIMERA1 OUT2.
B1OUT2 = 0xB - Trigger source is CTIMERB1 OUT2.
A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.
A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.
B2OUT2DUAL = 0xE - Trigger source is CTIMERB2 OUT2, dual edge.
A2OUT2DUAL = 0xF - Trigger source is CTIMERA2 OUT2, dual edge.
22 RSVD RO RESERVED

21:16 TMRB3LMT RW Counter/Timer B3 Pattern Limit Count.

15 RSVD RO RESERVED

14 TMRA3EN23 RW Counter/Timer A3 Upper compare enable.

DIS = 0x1 - Disable enhanced functions.
EN = 0x0 - Enable enhanced functions.
13 TMRA3POL23 RW Counter/Timer A3 Upper output polarity

NORM = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
12 TMRA3TINV RW Counter/Timer A3 Invert on trigger.

DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger
11 TMRA3NOSYNC RW Source clock synchronization control.

DIS = 0x0 - Synchronization on source clock
NOSYNC = 0x1 - No synchronization on source clock
10:7 TMRA3TRIG RW Counter/Timer A3 Trigger Select.

DIS = 0x0 - Trigger source is disabled.
B3OUT = 0x1 - Trigger source is CTIMERB3 OUT.
B2OUT = 0x2 - Trigger source is CTIMERB2 OUT.
A2OUT = 0x3 - Trigger source is CTIMERA2 OUT.
A4OUT = 0x4 - Trigger source is CTIMERA4 OUT.
B4OUT = 0x5 - Trigger source is CTIMERB4 OUT.
A7OUT = 0x6 - Trigger source is CTIMERA7 OUT.
B7OUT = 0x7 - Trigger source is CTIMERB7 OUT.
B5OUT2 = 0x8 - Trigger source is CTIMERB5 OUT2.
A5OUT2 = 0x9 - Trigger source is CTIMERA5 OUT2.
A1OUT2 = 0xA - Trigger source is CTIMERA1 OUT2.
B1OUT2 = 0xB - Trigger source is CTIMERB1 OUT2.
A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.
A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.
B2OUT2DUAL = 0xE - Trigger source is CTIMERB2 OUT2, dual edge.
A2OUT2DUAL = 0xF - Trigger source is CTIMERA2 OUT2, dual edge.
6:0 TMRA3LMT RW Counter/Timer A3 Pattern Limit Count.


TMR4 - Counter/Timer Register

Address:

  Instance 0 Address:   0x40008080

Description:

This register holds the running time or event count, either for each 16 bit half or for the whole 32 bit count when the pair is linked.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTTMRB4
0x0
CTTMRA4
0x0

Bits Name RW Description
31:16 CTTMRB4 RO Counter/Timer B4.

15:0 CTTMRA4 RO Counter/Timer A4.


CMPRA4 - Counter/Timer A4 Compare Registers

Address:

  Instance 0 Address:   0x40008084

Description:

Compare limits for timer half A.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1A4
0x0
CMPR0A4
0x0

Bits Name RW Description
31:16 CMPR1A4 RW Counter/Timer A4 Compare Register 1. Holds the upper limit for timer half A.

15:0 CMPR0A4 RW Counter/Timer A4 Compare Register 0. Holds the lower limit for timer half A.


CMPRB4 - Counter/Timer B4 Compare Registers

Address:

  Instance 0 Address:   0x40008088

Description:

Compare limits for timer half B.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1B4
0x0
CMPR0B4
0x0

Bits Name RW Description
31:16 CMPR1B4 RW Counter/Timer B4 Compare Register 1. Holds the upper limit for timer half B.

15:0 CMPR0B4 RW Counter/Timer B4 Compare Register 0. Holds the lower limit for timer half B.


CTRL4 - Counter/Timer Control

Address:

  Instance 0 Address:   0x4000808C

Description:

Control bit fields for both halves of timer 4.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTLINK4
0x0
RSVD
0x0
TMRB4POL
0x0
TMRB4CLR
0x0
TMRB4IE1
0x0
TMRB4IE0
0x0
TMRB4FN
0x0
TMRB4CLK
0x0
TMRB4EN
0x0
RSVD
0x0
TMRA4POL
0x0
TMRA4CLR
0x0
TMRA4IE1
0x0
TMRA4IE0
0x0
TMRA4FN
0x0
TMRA4CLK
0x0
TMRA4EN
0x0

Bits Name RW Description
31 CTLINK4 RW Counter/Timer A4/B4 Link bit.

TWO_16BIT_TIMERS = 0x0 - Use A4/B4 timers as two independent 16-bit timers (default).
32BIT_TIMER = 0x1 - Link A4/B4 timers into a single 32-bit timer.
30:29 RSVD RO RESERVED

28 TMRB4POL RW Counter/Timer B4 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINB4 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINB4 pin is the inverse of the timer output.
27 TMRB4CLR RW Counter/Timer B4 Clear bit.

RUN = 0x0 - Allow counter/timer B4 to run
CLEAR = 0x1 - Holds counter/timer B4 at 0x0000.
26 TMRB4IE1 RW Counter/Timer B4 Interrupt Enable bit for COMPR1.

DIS = 0x0 - Disable counter/timer B4 from generating an interrupt based on COMPR1.
EN = 0x1 - Enable counter/timer B4 to generate an interrupt based on COMPR1.
25 TMRB4IE0 RW Counter/Timer B4 Interrupt Enable bit for COMPR0.

DIS = 0x0 - Disable counter/timer B4 from generating an interrupt based on COMPR0.
EN = 0x1 - Enable counter/timer B4 to generate an interrupt based on COMPR0
24:22 TMRB4FN RW Counter/Timer B4 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B4, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B4, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B4, assert, count to CMPR1B4, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B4, assert, count to CMPR1B4, deassert, restart.
SINGLEPATTERN = 0x4 - Single pattern.
REPEATPATTERN = 0x5 - Repeated pattern.
CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously.
ALTPWN = 0x7 - Alternate PWM
21:17 TMRB4CLK RW Counter/Timer B4 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINB.
HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4
HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV128 = 0x9 - Clock source is XT / 128
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)
XT_DIV4 = 0x10 - Clock source is XT / 4
XT_DIV8 = 0x11 - Clock source is XT / 8
XT_DIV32 = 0x12 - Clock source is XT / 32
RSVD = 0x13 - Clock source is Reserved.
CTMRA4 = 0x14 - Clock source is CTIMERA4 OUT.
CTMRA1 = 0x15 - Clock source is CTIMERA1 OUT.
CTMRB1 = 0x16 - Clock source is CTIMERB1 OUT.
CTMRA5 = 0x17 - Clock source is CTIMERA5 OUT.
CTMRB5 = 0x18 - Clock source is CTIMERB5 OUT.
CTMRB0 = 0x19 - Clock source is CTIMERB0 OUT.
CTMRB2 = 0x1A - Clock source is CTIMERB2 OUT.
CTMRB3 = 0x1B - Clock source is CTIMERB3 OUT.
CTMRB6 = 0x1C - Clock source is CTIMERB6 OUT.
BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses.
BUCKB = 0x1E - Clock source is Memory buck converter TON pulses.
BUCKA = 0x1F - Clock source is CPU buck converter TON pulses.
16 TMRB4EN RW Counter/Timer B4 Enable bit.

DIS = 0x0 - Counter/Timer B4 Disable.
EN = 0x1 - Counter/Timer B4 Enable.
15:13 RSVD RO RESERVED

12 TMRA4POL RW Counter/Timer A4 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINA4 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINA4 pin is the inverse of the timer output.
11 TMRA4CLR RW Counter/Timer A4 Clear bit.

RUN = 0x0 - Allow counter/timer A4 to run
CLEAR = 0x1 - Holds counter/timer A4 at 0x0000.
10 TMRA4IE1 RW Counter/Timer A4 Interrupt Enable bit based on COMPR1.

DIS = 0x0 - Disable counter/timer A4 from generating an interrupt based on COMPR1.
EN = 0x1 - Enable counter/timer A4 to generate an interrupt based on COMPR1.
9 TMRA4IE0 RW Counter/Timer A4 Interrupt Enable bit based on COMPR0.

DIS = 0x0 - Disable counter/timer A4 from generating an interrupt based on COMPR0.
EN = 0x1 - Enable counter/timer A4 to generate an interrupt based on COMPR0.
8:6 TMRA4FN RW Counter/Timer A4 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A4, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A4, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A4, assert, count to CMPR1A4, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A4, assert, count to CMPR1A4, deassert, restart.
SINGLEPATTERN = 0x4 - Single pattern.
REPEATPATTERN = 0x5 - Repeated pattern.
CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously.
ALTPWN = 0x7 - Alternate PWM
5:1 TMRA4CLK RW Counter/Timer A4 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINA.
HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4
HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV128 = 0x9 - Clock source is XT / 128
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK_DIV4 = 0xF - Clock source is HCLK / 4. (note: this clock is only available when MCU is in active mode)
XT_DIV4 = 0x10 - Clock source is XT / 4
XT_DIV8 = 0x11 - Clock source is XT / 8
XT_DIV32 = 0x12 - Clock source is XT / 32
RSVD = 0x13 - Clock source is Reserved.
CTMRB4 = 0x14 - Clock source is CTIMERB4 OUT.
CTMRA1 = 0x15 - Clock source is CTIMERA1 OUT.
CTMRB1 = 0x16 - Clock source is CTIMERB1 OUT.
CTMRA5 = 0x17 - Clock source is CTIMERA5 OUT.
CTMRB5 = 0x18 - Clock source is CTIMERB5 OUT.
CTMRB0 = 0x19 - Clock source is CTIMERB0 OUT.
CTMRB2 = 0x1A - Clock source is CTIMERB2 OUT.
CTMRB3 = 0x1B - Clock source is CTIMERB3 OUT.
CTMRB6 = 0x1C - Clock source is CTIMERB6 OUT.
BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses.
BUCKB = 0x1E - Clock source is Memory buck converter TON pulses.
BUCKA = 0x1F - Clock source is CPU buck converter TON pulses.
0 TMRA4EN RW Counter/Timer A4 Enable bit.

DIS = 0x0 - Counter/Timer A4 Disable.
EN = 0x1 - Counter/Timer A4 Enable.

CMPRAUXA4 - Counter/Timer A4 Compare Registers

Address:

  Instance 0 Address:   0x40008094

Description:

Enhanced compare limits for timer half A.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR3A4
0x0
CMPR2A4
0x0

Bits Name RW Description
31:16 CMPR3A4 RW Counter/Timer A4 Compare Register 3. Holds the upper limit for timer half A.

15:0 CMPR2A4 RW Counter/Timer A4 Compare Register 2. Holds the lower limit for timer half A.


CMPRAUXB4 - Counter/Timer B4 Compare Registers

Address:

  Instance 0 Address:   0x40008098

Description:

Enhanced compare limits for timer half B.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR3B4
0x0
CMPR2B4
0x0

Bits Name RW Description
31:16 CMPR3B4 RW Counter/Timer B4 Compare Register 3. Holds the upper limit for timer half B.

15:0 CMPR2B4 RW Counter/Timer B4 Compare Register 2. Holds the lower limit for timer half B.


AUX4 - Counter/Timer Auxiliary

Address:

  Instance 0 Address:   0x4000809C

Description:

Control bit fields for both halves of timer 4.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
TMRB4EN23
0x0
TMRB4POL23
0x0
TMRB4TINV
0x0
TMRB4NOSYNC
0x0
TMRB4TRIG
0x0
RSVD
0x0
TMRB4LMT
0x0
RSVD
0x0
TMRA4EN23
0x0
TMRA4POL23
0x0
TMRA4TINV
0x0
TMRA4NOSYNC
0x0
TMRA4TRIG
0x0
TMRA4LMT
0x0

Bits Name RW Description
31 RSVD RO RESERVED

30 TMRB4EN23 RW Counter/Timer B4 Upper compare enable.

DIS = 0x1 - Disable enhanced functions.
EN = 0x0 - Enable enhanced functions.
29 TMRB4POL23 RW Upper output polarity

NORM = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
28 TMRB4TINV RW Counter/Timer B4 Invert on trigger.

DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger
27 TMRB4NOSYNC RW Source clock synchronization control.

DIS = 0x0 - Synchronization on source clock
NOSYNC = 0x1 - No synchronization on source clock
26:23 TMRB4TRIG RW Counter/Timer B4 Trigger Select.

DIS = 0x0 - Trigger source is disabled.
A4OUT = 0x1 - Trigger source is CTIMERA4 OUT.
B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
A3OUT = 0x3 - Trigger source is CTIMERA3 OUT.
A7OUT = 0x4 - Trigger source is CTIMERA7 OUT.
B7OUT = 0x5 - Trigger source is CTIMERB7 OUT.
A1OUT = 0x6 - Trigger source is CTIMERA1 OUT.
B1OUT = 0x7 - Trigger source is CTIMERB1 OUT.
B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2.
A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2.
A1OUT2 = 0xA - Trigger source is CTIMERA1 OUT2.
B1OUT2 = 0xB - Trigger source is CTIMERB1 OUT2.
A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.
A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.
B5OUT2DUAL = 0xE - Trigger source is CTIMERB5 OUT2, dual edge.
A5OUT2DUAL = 0xF - Trigger source is CTIMERA5 OUT2, dual edge.
STIMERCAP0 = 0x4 - Trigger source is STimer Capture0 Interrupt. When CTLINK==1 and TMRA4TRIG==1. (Apollo3 - B0)
STIMERCAP1 = 0x5 - Trigger source is STimer Capture1 Interrupt. When CTLINK==1 and TMRA4TRIG==1. (Apollo3 - B0)
STIMERCAP2 = 0x6 - Trigger source is STimer Capture2 Interrupt. When CTLINK==1 and TMRA4TRIG==1. (Apollo3 - B0)
STIMERCAP3 = 0x7 - Trigger source is STimer Capture3 Interrupt. When CTLINK==1 and TMRA4TRIG==1. (Apollo3 - B0)
STIMERCMP0 = 0x8 - Trigger source is STimer Compare0 Interrupt. When CTLINK==1 and TMRA4TRIG==1. (Apollo3 - B0)
STIMERCMP1 = 0x9 - Trigger source is STimer Compare1 Interrupt. When CTLINK==1 and TMRA4TRIG==1. (Apollo3 - B0)
STIMERCMP2 = 0xA - Trigger source is STimer Compare2 Interrupt. When CTLINK==1 and TMRA4TRIG==1. (Apollo3 - B0)
STIMERCMP3 = 0xB - Trigger source is STimer Compare3 Interrupt. When CTLINK==1 and TMRA4TRIG==1. (Apollo3 - B0)
STIMERCMP4 = 0xC - Trigger source is STimer Compare4 Interrupt. When CTLINK==1 and TMRA4TRIG==1. (Apollo3 - B0)
STIMERCMP5 = 0xD - Trigger source is STimer Compare5 Interrupt. When CTLINK==1 and TMRA4TRIG==1. (Apollo3 - B0)
STIMERCMP6 = 0xE - Trigger source is STimer Compare6 Interrupt. When CTLINK==1 and TMRA4TRIG==1. (Apollo3 - B0)
STIMERCMP7 = 0xF - Trigger source is STimer Compare7 Interrupt. When CTLINK==1 and TMRA4TRIG==1. (Apollo3 - B0)
22 RSVD RO RESERVED

21:16 TMRB4LMT RW Counter/Timer B4 Pattern Limit Count.

15 RSVD RO RESERVED

14 TMRA4EN23 RW Counter/Timer A4 Upper compare enable.

DIS = 0x1 - Disable enhanced functions.
EN = 0x0 - Enable enhanced functions.
13 TMRA4POL23 RW Counter/Timer A4 Upper output polarity

NORM = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
12 TMRA4TINV RW Counter/Timer A4 Invert on trigger.

DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger
11 TMRA4NOSYNC RW Source clock synchronization control.

DIS = 0x0 - Synchronization on source clock
NOSYNC = 0x1 - No synchronization on source clock
10:7 TMRA4TRIG RW Counter/Timer A4 Trigger Select.

DIS = 0x0 - Trigger source is disabled.
STIMER = 0x1 - Trigger source is STimer Interrupt. Only Active When CTLINK==1 and TMRB4TRIG!=0. TMRB4TRIG selects an STIMER interrupt
B4OUT = 0x1 - Trigger source is CTIMERB4 OUT.
B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
A3OUT = 0x3 - Trigger source is CTIMERA3 OUT.
A6OUT = 0x4 - Trigger source is CTIMERA6 OUT.
B6OUT = 0x5 - Trigger source is CTIMERB6 OUT.
A2OUT = 0x6 - Trigger source is CTIMERA2 OUT.
B2OUT = 0x7 - Trigger source is CTIMERB2 OUT.
B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2.
A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2.
A1OUT2 = 0xA - Trigger source is CTIMERA1 OUT2.
B1OUT2 = 0xB - Trigger source is CTIMERB1 OUT2.
A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.
A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.
B5OUT2DUAL = 0xE - Trigger source is CTIMERB5 OUT2, dual edge.
A5OUT2DUAL = 0xF - Trigger source is CTIMERA5 OUT2, dual edge.
6:0 TMRA4LMT RW Counter/Timer A4 Pattern Limit Count.


TMR5 - Counter/Timer Register

Address:

  Instance 0 Address:   0x400080A0

Description:

This register holds the running time or event count, either for each 16 bit half or for the whole 32 bit count when the pair is linked.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTTMRB5
0x0
CTTMRA5
0x0

Bits Name RW Description
31:16 CTTMRB5 RO Counter/Timer B5.

15:0 CTTMRA5 RO Counter/Timer A5.


CMPRA5 - Counter/Timer A5 Compare Registers

Address:

  Instance 0 Address:   0x400080A4

Description:

This register holds the compare limits for timer half A.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1A5
0x0
CMPR0A5
0x0

Bits Name RW Description
31:16 CMPR1A5 RW Counter/Timer A5 Compare Register 1.

15:0 CMPR0A5 RW Counter/Timer A5 Compare Register 0.


CMPRB5 - Counter/Timer B5 Compare Registers

Address:

  Instance 0 Address:   0x400080A8

Description:

This register holds the compare limits for timer half B.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1B5
0x0
CMPR0B5
0x0

Bits Name RW Description
31:16 CMPR1B5 RW Counter/Timer B5 Compare Register 1.

15:0 CMPR0B5 RW Counter/Timer B5 Compare Register 0.


CTRL5 - Counter/Timer Control

Address:

  Instance 0 Address:   0x400080AC

Description:

Control bit fields for both halves of timer 0.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTLINK5
0x0
RSVD
0x0
TMRB5POL
0x0
TMRB5CLR
0x0
TMRB5IE1
0x0
TMRB5IE0
0x0
TMRB5FN
0x0
TMRB5CLK
0x0
TMRB5EN
0x0
RSVD
0x0
TMRA5POL
0x0
TMRA5CLR
0x0
TMRA5IE1
0x0
TMRA5IE0
0x0
TMRA5FN
0x0
TMRA5CLK
0x0
TMRA5EN
0x0

Bits Name RW Description
31 CTLINK5 RW Counter/Timer A5/B5 Link bit.

TWO_16BIT_TIMERS = 0x0 - Use A5/B5 timers as two independent 16-bit timers (default).
32BIT_TIMER = 0x1 - Link A5/B5 timers into a single 32-bit timer.
30:29 RSVD RO RESERVED

28 TMRB5POL RW Counter/Timer B5 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINB5 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINB5 pin is the inverse of the timer output.
27 TMRB5CLR RW Counter/Timer B5 Clear bit.

RUN = 0x0 - Allow counter/timer B5 to run
CLEAR = 0x1 - Holds counter/timer B5 at 0x0000.
26 TMRB5IE1 RW Counter/Timer B5 Interrupt Enable bit for COMPR1.

DIS = 0x0 - Disable counter/timer B5 from generating an interrupt based on COMPR1.
EN = 0x1 - Enable counter/timer B5 to generate an interrupt based on COMPR1.
25 TMRB5IE0 RW Counter/Timer B5 Interrupt Enable bit for COMPR0.

DIS = 0x0 - Disable counter/timer B5 from generating an interrupt based on COMPR0.
EN = 0x1 - Enable counter/timer B5 to generate an interrupt based on COMPR0
24:22 TMRB5FN RW Counter/Timer B5 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B5, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B5, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B5, assert, count to CMPR1B5, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B5, assert, count to CMPR1B5, deassert, restart.
SINGLEPATTERN = 0x4 - Single pattern.
REPEATPATTERN = 0x5 - Repeated pattern.
CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously.
ALTPWN = 0x7 - Alternate PWM
21:17 TMRB5CLK RW Counter/Timer B5 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINB.
HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4
HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV128 = 0x9 - Clock source is XT / 128
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)
XT_DIV4 = 0x10 - Clock source is XT / 4
XT_DIV8 = 0x11 - Clock source is XT / 8
XT_DIV32 = 0x12 - Clock source is XT / 32
RSVD = 0x13 - Clock source is Reserved.
CTMRA5 = 0x14 - Clock source is CTIMERA5 OUT.
CTMRA0 = 0x15 - Clock source is CTIMERA0 OUT.
CTMRB0 = 0x16 - Clock source is CTIMERB0 OUT.
CTMRA6 = 0x17 - Clock source is CTIMERA6 OUT.
CTMRB6 = 0x18 - Clock source is CTIMERB6 OUT.
CTMRB1 = 0x19 - Clock source is CTIMERB1 OUT.
CTMRB2 = 0x1A - Clock source is CTIMERB2 OUT.
CTMRB3 = 0x1B - Clock source is CTIMERB3 OUT.
CTMRB4 = 0x1C - Clock source is CTIMERB4 OUT.
BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses.
BUCKB = 0x1E - Clock source is Memory buck converter TON pulses.
BUCKA = 0x1F - Clock source is CPU buck converter TON pulses.
16 TMRB5EN RW Counter/Timer B5 Enable bit.

DIS = 0x0 - Counter/Timer B5 Disable.
EN = 0x1 - Counter/Timer B5 Enable.
15:13 RSVD RO RESERVED

12 TMRA5POL RW Counter/Timer A5 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINA5 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINA5 pin is the inverse of the timer output.
11 TMRA5CLR RW Counter/Timer A5 Clear bit.

RUN = 0x0 - Allow counter/timer A5 to run
CLEAR = 0x1 - Holds counter/timer A5 at 0x0000.
10 TMRA5IE1 RW Counter/Timer A5 Interrupt Enable bit based on COMPR1.

DIS = 0x0 - Disable counter/timer A5 from generating an interrupt based on COMPR1.
EN = 0x1 - Enable counter/timer A5 to generate an interrupt based on COMPR1.
9 TMRA5IE0 RW Counter/Timer A5 Interrupt Enable bit based on COMPR0.

DIS = 0x0 - Disable counter/timer A5 from generating an interrupt based on COMPR0.
EN = 0x1 - Enable counter/timer A5 to generate an interrupt based on COMPR0.
8:6 TMRA5FN RW Counter/Timer A5 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A5, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A5, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A5, assert, count to CMPR1A5, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A5, assert, count to CMPR1A5, deassert, restart.
SINGLEPATTERN = 0x4 - Single pattern.
REPEATPATTERN = 0x5 - Repeated pattern.
CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously.
ALTPWN = 0x7 - Alternate PWM
TRIGCOPY = 0x7 - Replicate the trigger input
DUALTRIGPATTERN = 0x4 - Single pattern, trigger on either edge.
5:1 TMRA5CLK RW Counter/Timer A5 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINA.
HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4
HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV128 = 0x9 - Clock source is XT / 128
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)
XT_DIV4 = 0x10 - Clock source is XT / 4
XT_DIV8 = 0x11 - Clock source is XT / 8
XT_DIV32 = 0x12 - Clock source is XT / 32
RSVD = 0x13 - Clock source is Reserved.
CTMRB5 = 0x14 - Clock source is CTIMERB5 OUT.
CTMRA0 = 0x15 - Clock source is CTIMERA0 OUT.
CTMRB0 = 0x16 - Clock source is CTIMERB0 OUT.
CTMRA6 = 0x17 - Clock source is CTIMERA6 OUT.
CTMRB6 = 0x18 - Clock source is CTIMERB6 OUT.
CTMRB1 = 0x19 - Clock source is CTIMERB1 OUT.
CTMRB2 = 0x1A - Clock source is CTIMERB2 OUT.
CTMRB3 = 0x1B - Clock source is CTIMERB3 OUT.
CTMRB4 = 0x1C - Clock source is CTIMERB4 OUT.
BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses.
BUCKB = 0x1E - Clock source is Memory buck converter TON pulses.
BUCKA = 0x1F - Clock source is CPU buck converter TON pulses.
0 TMRA5EN RW Counter/Timer A5 Enable bit.

DIS = 0x0 - Counter/Timer A5 Disable.
EN = 0x1 - Counter/Timer A5 Enable.

CMPRAUXA5 - Counter/Timer A5 Compare Registers

Address:

  Instance 0 Address:   0x400080B4

Description:

Enhanced compare limits for timer half A.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR3A5
0x0
CMPR2A5
0x0

Bits Name RW Description
31:16 CMPR3A5 RW Counter/Timer A5 Compare Register 3. Holds the upper limit for timer half A.

15:0 CMPR2A5 RW Counter/Timer A5 Compare Register 2. Holds the lower limit for timer half A.


CMPRAUXB5 - Counter/Timer B5 Compare Registers

Address:

  Instance 0 Address:   0x400080B8

Description:

Enhanced compare limits for timer half B.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR3B5
0x0
CMPR2B5
0x0

Bits Name RW Description
31:16 CMPR3B5 RW Counter/Timer B5 Compare Register 3. Holds the upper limit for timer half B.

15:0 CMPR2B5 RW Counter/Timer B5 Compare Register 2. Holds the lower limit for timer half B.


AUX5 - Counter/Timer Auxiliary

Address:

  Instance 0 Address:   0x400080BC

Description:

Control bit fields for both halves of timer 0.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
TMRB5EN23
0x0
TMRB5POL23
0x0
TMRB5TINV
0x0
TMRB5NOSYNC
0x0
TMRB5TRIG
0x0
RSVD
0x0
TMRB5LMT
0x0
RSVD
0x0
TMRA5EN23
0x0
TMRA5POL23
0x0
TMRA5TINV
0x0
TMRA5NOSYNC
0x0
TMRA5TRIG
0x0
TMRA5LMT
0x0

Bits Name RW Description
31 RSVD RO RESERVED

30 TMRB5EN23 RW Counter/Timer B5 Upper compare enable.

DIS = 0x1 - Disable enhanced functions.
EN = 0x0 - Enable enhanced functions.
29 TMRB5POL23 RW Upper output polarity

NORM = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
28 TMRB5TINV RW Counter/Timer B5 Invert on trigger.

DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger
27 TMRB5NOSYNC RW Source clock synchronization control.

DIS = 0x0 - Synchronization on source clock
NOSYNC = 0x1 - No synchronization on source clock
26:23 TMRB5TRIG RW Counter/Timer B5 Trigger Select.

DIS = 0x0 - Trigger source is disabled.
A5OUT = 0x1 - Trigger source is CTIMERA5 OUT.
B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
A3OUT = 0x3 - Trigger source is CTIMERA3 OUT.
A6OUT = 0x4 - Trigger source is CTIMERA6 OUT.
B6OUT = 0x5 - Trigger source is CTIMERB6 OUT.
A1OUT = 0x6 - Trigger source is CTIMERA1 OUT.
B1OUT = 0x7 - Trigger source is CTIMERB1 OUT.
B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2.
A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2.
A0OUT2 = 0xA - Trigger source is CTIMERA0 OUT2.
B0OUT2 = 0xB - Trigger source is CTIMERB0 OUT2.
A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.
A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.
B4OUT2DUAL = 0xE - Trigger source is CTIMERB4 OUT2, dual edge.
A4OUT2DUAL = 0xF - Trigger source is CTIMERA4 OUT2, dual edge.
STIMERCAP0 = 0x4 - Trigger source is STimer Capture0 Interrupt. When CTLINK==1 and TMRA5TRIG==1. (Apollo3 - B0)
STIMERCAP1 = 0x5 - Trigger source is STimer Capture1 Interrupt. When CTLINK==1 and TMRA5TRIG==1. (Apollo3 - B0)
STIMERCAP2 = 0x6 - Trigger source is STimer Capture2 Interrupt. When CTLINK==1 and TMRA5TRIG==1. (Apollo3 - B0)
STIMERCAP3 = 0x7 - Trigger source is STimer Capture3 Interrupt. When CTLINK==1 and TMRA5TRIG==1. (Apollo3 - B0)
STIMERCMP0 = 0x8 - Trigger source is STimer Compare0 Interrupt. When CTLINK==1 and TMRA5TRIG==1. (Apollo3 - B0)
STIMERCMP1 = 0x9 - Trigger source is STimer Compare1 Interrupt. When CTLINK==1 and TMRA5TRIG==1. (Apollo3 - B0)
STIMERCMP2 = 0xA - Trigger source is STimer Compare2 Interrupt. When CTLINK==1 and TMRA5TRIG==1. (Apollo3 - B0)
STIMERCMP3 = 0xB - Trigger source is STimer Compare3 Interrupt. When CTLINK==1 and TMRA5TRIG==1. (Apollo3 - B0)
STIMERCMP4 = 0xC - Trigger source is STimer Compare4 Interrupt. When CTLINK==1 and TMRA5TRIG==1. (Apollo3 - B0)
STIMERCMP5 = 0xD - Trigger source is STimer Compare5 Interrupt. When CTLINK==1 and TMRA5TRIG==1. (Apollo3 - B0)
STIMERCMP6 = 0xE - Trigger source is STimer Compare6 Interrupt. When CTLINK==1 and TMRA5TRIG==1. (Apollo3 - B0)
STIMERCMP7 = 0xF - Trigger source is STimer Compare7 Interrupt. When CTLINK==1 and TMRA5TRIG==1. (Apollo3 - B0)
22 RSVD RO RESERVED

21:16 TMRB5LMT RW Counter/Timer B5 Pattern Limit Count.

15 RSVD RO RESERVED

14 TMRA5EN23 RW Counter/Timer A5 Upper compare enable.

DIS = 0x1 - Disable enhanced functions.
EN = 0x0 - Enable enhanced functions.
13 TMRA5POL23 RW Counter/Timer A5 Upper output polarity

NORMAL = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
12 TMRA5TINV RW Counter/Timer A5 Invert on trigger.

DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger
11 TMRA5NOSYNC RW Source clock synchronization control.

DIS = 0x0 - Synchronization on source clock
NOSYNC = 0x1 - No synchronization on source clock
10:7 TMRA5TRIG RW Counter/Timer A5 Trigger Select.

DIS = 0x0 - Trigger source is disabled.
STIMER = 0x1 - Trigger source is STimer Interrupt. Only Active When CTLINK==1 and TMRB5TRIG!=0. TMRB5TRIG selects an STIMER interrupt
B5OUT = 0x1 - Trigger source is CTIMERB5 OUT.
B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
A3OUT = 0x3 - Trigger source is CTIMERA3 OUT.
A4OUT = 0x4 - Trigger source is CTIMERA4 OUT.
B4OUT = 0x5 - Trigger source is CTIMERB4 OUT.
A2OUT = 0x6 - Trigger source is CTIMERA2 OUT.
B2OUT = 0x7 - Trigger source is CTIMERB2 OUT.
B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2.
A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2.
A0OUT2 = 0xA - Trigger source is CTIMERA0 OUT2.
B0OUT2 = 0xB - Trigger source is CTIMERB0 OUT2.
A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.
A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.
B4OUT2DUAL = 0xE - Trigger source is CTIMERB4 OUT2, dual edge.
A4OUT2DUAL = 0xF - Trigger source is CTIMERA4 OUT2, dual edge.
6:0 TMRA5LMT RW Counter/Timer A5 Pattern Limit Count.


TMR6 - Counter/Timer Register

Address:

  Instance 0 Address:   0x400080C0

Description:

Counter/Timer Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTTMRB6
0x0
CTTMRA6
0x0

Bits Name RW Description
31:16 CTTMRB6 RO Counter/Timer B6.

15:0 CTTMRA6 RO Counter/Timer A6.


CMPRA6 - Counter/Timer A6 Compare Registers

Address:

  Instance 0 Address:   0x400080C4

Description:

This register holds the compare limits for timer half A.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1A6
0x0
CMPR0A6
0x0

Bits Name RW Description
31:16 CMPR1A6 RW Counter/Timer A6 Compare Register 1.

15:0 CMPR0A6 RW Counter/Timer A6 Compare Register 0.


CMPRB6 - Counter/Timer B6 Compare Registers

Address:

  Instance 0 Address:   0x400080C8

Description:

This register holds the compare limits for timer half B.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1B6
0x0
CMPR0B6
0x0

Bits Name RW Description
31:16 CMPR1B6 RW Counter/Timer B6 Compare Register 1.

15:0 CMPR0B6 RW Counter/Timer B6 Compare Register 0.


CTRL6 - Counter/Timer Control

Address:

  Instance 0 Address:   0x400080CC

Description:

This register holds the control bit fields for both halves of timer 6.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTLINK6
0x0
RSVD
0x0
TMRB6POL
0x0
TMRB6CLR
0x0
TMRB6IE1
0x0
TMRB6IE0
0x0
TMRB6FN
0x0
TMRB6CLK
0x0
TMRB6EN
0x0
RSVD
0x0
TMRA6POL
0x0
TMRA6CLR
0x0
TMRA6IE1
0x0
TMRA6IE0
0x0
TMRA6FN
0x0
TMRA6CLK
0x0
TMRA6EN
0x0

Bits Name RW Description
31 CTLINK6 RW Counter/Timer A6/B6 Link bit.

TWO_16BIT_TIMERS = 0x0 - Use A6/B6 timers as two independent 16-bit timers (default).
32BIT_TIMER = 0x1 - Link A6/B6 timers into a single 32-bit timer.
30:29 RSVD RO RESERVED

28 TMRB6POL RW Counter/Timer B6 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINB6 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINB6 pin is the inverse of the timer output.
27 TMRB6CLR RW Counter/Timer B6 Clear bit.

RUN = 0x0 - Allow counter/timer B6 to run
CLEAR = 0x1 - Holds counter/timer B6 at 0x0000.
26 TMRB6IE1 RW Counter/Timer B6 Interrupt Enable bit for COMPR1.

DIS = 0x0 - Disable counter/timer B6 from generating an interrupt based on COMPR1.
EN = 0x1 - Enable counter/timer B6 to generate an interrupt based on COMPR1.
25 TMRB6IE0 RW Counter/Timer B6 Interrupt Enable bit for COMPR0.

DIS = 0x0 - Disable counter/timer B6 from generating an interrupt based on COMPR0.
EN = 0x1 - Enable counter/timer B6 to generate an interrupt based on COMPR0
24:22 TMRB6FN RW Counter/Timer B6 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B6, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B6, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B6, assert, count to CMPR1B6, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B6, assert, count to CMPR1B6, deassert, restart.
SINGLEPATTERN = 0x4 - Single pattern.
REPEATPATTERN = 0x5 - Repeated pattern.
CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously.
ALTPWN = 0x7 - Alternate PWM
21:17 TMRB6CLK RW Counter/Timer B6 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINB.
HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4
HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV128 = 0x9 - Clock source is XT / 128
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)
XT_DIV4 = 0x10 - Clock source is XT / 4
XT_DIV8 = 0x11 - Clock source is XT / 8
XT_DIV32 = 0x12 - Clock source is XT / 32
RSVD = 0x13 - Clock source is Reserved.
CTMRA6 = 0x14 - Clock source is CTIMERA6 OUT.
CTMRA3 = 0x15 - Clock source is CTIMERA3 OUT.
CTMRB3 = 0x16 - Clock source is CTIMERB3 OUT.
CTMRA7 = 0x17 - Clock source is CTIMERA7 OUT.
CTMRB7 = 0x18 - Clock source is CTIMERB7 OUT.
CTMRB0 = 0x19 - Clock source is CTIMERB0 OUT.
CTMRB1 = 0x1A - Clock source is CTIMERB1 OUT.
CTMRB2 = 0x1B - Clock source is CTIMERB2 OUT.
CTMRB4 = 0x1C - Clock source is CTIMERB4 OUT.
BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses.
BUCKB = 0x1E - Clock source is Memory buck converter TON pulses.
BUCKA = 0x1F - Clock source is CPU buck converter TON pulses.
16 TMRB6EN RW Counter/Timer B6 Enable bit.

DIS = 0x0 - Counter/Timer B6 Disable.
EN = 0x1 - Counter/Timer B6 Enable.
15:13 RSVD RO RESERVED

12 TMRA6POL RW Counter/Timer A6 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINA6 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINA6 pin is the inverse of the timer output.
11 TMRA6CLR RW Counter/Timer A6 Clear bit.

RUN = 0x0 - Allow counter/timer A6 to run
CLEAR = 0x1 - Holds counter/timer A6 at 0x0000.
10 TMRA6IE1 RW Counter/Timer A6 Interrupt Enable bit based on COMPR1.

DIS = 0x0 - Disable counter/timer A6 from generating an interrupt based on COMPR1.
EN = 0x1 - Enable counter/timer A6 to generate an interrupt based on COMPR1.
9 TMRA6IE0 RW Counter/Timer A6 Interrupt Enable bit based on COMPR0.

DIS = 0x0 - Disable counter/timer A6 from generating an interrupt based on COMPR0.
EN = 0x1 - Enable counter/timer A6 to generate an interrupt based on COMPR0.
8:6 TMRA6FN RW Counter/Timer A6 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A6, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A6, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A6, assert, count to CMPR1A6, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A6, assert, count to CMPR1A6, deassert, restart.
SINGLEPATTERN = 0x4 - Single pattern.
REPEATPATTERN = 0x5 - Repeated pattern.
CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously.
ALTPWN = 0x7 - Alternate PWM
5:1 TMRA6CLK RW Counter/Timer A6 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINA.
HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4
HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV128 = 0x9 - Clock source is XT / 128
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)
XT_DIV4 = 0x10 - Clock source is XT / 4
XT_DIV8 = 0x11 - Clock source is XT / 8
XT_DIV32 = 0x12 - Clock source is XT / 32
RSVD = 0x13 - Clock source is Reserved.
CTMRB6 = 0x14 - Clock source is CTIMERB6 OUT.
CTMRA3 = 0x15 - Clock source is CTIMERA3 OUT.
CTMRB3 = 0x16 - Clock source is CTIMERB3 OUT.
CTMRA7 = 0x17 - Clock source is CTIMERA7 OUT.
CTMRB7 = 0x18 - Clock source is CTIMERB7 OUT.
CTMRB0 = 0x19 - Clock source is CTIMERB0 OUT.
CTMRB1 = 0x1A - Clock source is CTIMERB1 OUT.
CTMRB2 = 0x1B - Clock source is CTIMERB2 OUT.
CTMRB4 = 0x1C - Clock source is CTIMERB4 OUT.
BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses.
BUCKB = 0x1E - Clock source is Memory buck converter TON pulses.
BUCKA = 0x1F - Clock source is CPU buck converter TON pulses.
0 TMRA6EN RW Counter/Timer A6 Enable bit.

DIS = 0x0 - Counter/Timer A6 Disable.
EN = 0x1 - Counter/Timer A6 Enable.

CMPRAUXA6 - Counter/Timer A6 Compare Registers

Address:

  Instance 0 Address:   0x400080D4

Description:

Enhanced compare limits for timer half A.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR3A6
0x0
CMPR2A6
0x0

Bits Name RW Description
31:16 CMPR3A6 RW Counter/Timer A6 Compare Register 3. Holds the upper limit for timer half A.

15:0 CMPR2A6 RW Counter/Timer A6 Compare Register 2. Holds the lower limit for timer half A.


CMPRAUXB6 - Counter/Timer B6 Compare Registers

Address:

  Instance 0 Address:   0x400080D8

Description:

Enhanced compare limits for timer half B.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR3B6
0x0
CMPR2B6
0x0

Bits Name RW Description
31:16 CMPR3B6 RW Counter/Timer B6 Compare Register 3. Holds the upper limit for timer half B.

15:0 CMPR2B6 RW Counter/Timer B6 Compare Register 2. Holds the lower limit for timer half B.


AUX6 - Counter/Timer Auxiliary

Address:

  Instance 0 Address:   0x400080DC

Description:

Control bit fields for both halves of timer 0.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
TMRB6EN23
0x0
TMRB6POL23
0x0
TMRB6TINV
0x0
TMRB6NOSYNC
0x0
TMRB6TRIG
0x0
RSVD
0x0
TMRB6LMT
0x0
RSVD
0x0
TMRA6EN23
0x0
TMRA6POL23
0x0
TMRA6TINV
0x0
TMRA6NOSYNC
0x0
TMRA6TRIG
0x0
TMRA6LMT
0x0

Bits Name RW Description
31 RSVD RO RESERVED

30 TMRB6EN23 RW Counter/Timer B6 Upper compare enable.

DIS = 0x1 - Disable enhanced functions.
EN = 0x0 - Enable enhanced functions.
29 TMRB6POL23 RW Upper output polarity

NORM = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
28 TMRB6TINV RW Counter/Timer B6 Invert on trigger.

DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger
27 TMRB6NOSYNC RW Source clock synchronization control.

DIS = 0x0 - Synchronization on source clock
NOSYNC = 0x1 - No synchronization on source clock
26:23 TMRB6TRIG RW Counter/Timer B6 Trigger Select.

DIS = 0x0 - Trigger source is disabled.
A6OUT = 0x1 - Trigger source is CTIMERA6 OUT.
B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
A3OUT = 0x3 - Trigger source is CTIMERA3 OUT.
A4OUT = 0x4 - Trigger source is CTIMERA4 OUT.
B4OUT = 0x5 - Trigger source is CTIMERB4 OUT.
A1OUT = 0x6 - Trigger source is CTIMERA1 OUT.
B1OUT = 0x7 - Trigger source is CTIMERB1 OUT.
B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2.
A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2.
A2OUT2 = 0xA - Trigger source is CTIMERA2 OUT2.
B2OUT2 = 0xB - Trigger source is CTIMERB2 OUT2.
A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.
A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.
B0OUT2DUAL = 0xE - Trigger source is CTIMERB0 OUT2, dual edge.
A0OUT2DUAL = 0xF - Trigger source is CTIMERA0 OUT2, dual edge.
22 RSVD RO RESERVED

21:16 TMRB6LMT RW Counter/Timer B6 Pattern Limit Count.

15 RSVD RO RESERVED

14 TMRA6EN23 RW Counter/Timer A6 Upper compare enable.

DIS = 0x1 - Disable enhanced functions.
EN = 0x0 - Enable enhanced functions.
13 TMRA6POL23 RW Counter/Timer A6 Upper output polarity

NORM = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
12 TMRA6TINV RW Counter/Timer A6 Invert on trigger.

DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger
11 TMRA6NOSYNC RW Source clock synchronization control.

DIS = 0x0 - Synchronization on source clock
NOSYNC = 0x1 - No synchronization on source clock
10:7 TMRA6TRIG RW Counter/Timer A6 Trigger Select.

DIS = 0x0 - Trigger source is disabled.
B6OUT = 0x1 - Trigger source is CTIMERB6 OUT.
B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
A3OUT = 0x3 - Trigger source is CTIMERA3 OUT.
A5OUT = 0x4 - Trigger source is CTIMERA5 OUT.
B5OUT = 0x5 - Trigger source is CTIMERB5 OUT.
A1OUT = 0x6 - Trigger source is CTIMERA1 OUT.
B1OUT = 0x7 - Trigger source is CTIMERB1 OUT.
B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2.
A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2.
A2OUT2 = 0xA - Trigger source is CTIMERA2 OUT2.
B2OUT2 = 0xB - Trigger source is CTIMERBb OUT2.
A5OUT2DUAL = 0xC - Trigger source is CTIMERA5 OUT2, dual edge.
A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.
B0OUT2DUAL = 0xE - Trigger source is CTIMERB0 OUT2, dual edge.
A0OUT2DUAL = 0xF - Trigger source is CTIMERA0 OUT2, dual edge.
6:0 TMRA6LMT RW Counter/Timer A6 Pattern Limit Count.


TMR7 - Counter/Timer Register

Address:

  Instance 0 Address:   0x400080E0

Description:

Counter/Timer Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTTMRB7
0x0
CTTMRA7
0x0

Bits Name RW Description
31:16 CTTMRB7 RO Counter/Timer B7.

15:0 CTTMRA7 RO Counter/Timer A7.


CMPRA7 - Counter/Timer A7 Compare Registers

Address:

  Instance 0 Address:   0x400080E4

Description:

This register holds the compare limits for timer half A.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1A7
0x0
CMPR0A7
0x0

Bits Name RW Description
31:16 CMPR1A7 RW Counter/Timer A7 Compare Register 1.

15:0 CMPR0A7 RW Counter/Timer A7 Compare Register 0.


CMPRB7 - Counter/Timer B7 Compare Registers

Address:

  Instance 0 Address:   0x400080E8

Description:

This register holds the compare limits for timer half B.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1B7
0x0
CMPR0B7
0x0

Bits Name RW Description
31:16 CMPR1B7 RW Counter/Timer B3 Compare Register 1.

15:0 CMPR0B7 RW Counter/Timer B3 Compare Register 0.


CTRL7 - Counter/Timer Control

Address:

  Instance 0 Address:   0x400080EC

Description:

This register holds the control bit fields for both halves of timer 7.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTLINK7
0x0
RSVD
0x0
TMRB7POL
0x0
TMRB7CLR
0x0
TMRB7IE1
0x0
TMRB7IE0
0x0
TMRB7FN
0x0
TMRB7CLK
0x0
TMRB7EN
0x0
RSVD
0x0
TMRA7POL
0x0
TMRA7CLR
0x0
TMRA7IE1
0x0
TMRA7IE0
0x0
TMRA7FN
0x0
TMRA7CLK
0x0
TMRA7EN
0x0

Bits Name RW Description
31 CTLINK7 RW Counter/Timer A7/B7 Link bit.

TWO_16BIT_TIMERS = 0x0 - Use A7/B7 timers as two independent 16-bit timers (default).
32BIT_TIMER = 0x1 - Link A7/B7 timers into a single 32-bit timer.
30:29 RSVD RO RESERVED

28 TMRB7POL RW Counter/Timer B7 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINB7 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINB7 pin is the inverse of the timer output.
27 TMRB7CLR RW Counter/Timer B7 Clear bit.

RUN = 0x0 - Allow counter/timer B7 to run
CLEAR = 0x1 - Holds counter/timer B7 at 0x0000.
26 TMRB7IE1 RW Counter/Timer B7 Interrupt Enable bit for COMPR1.

DIS = 0x0 - Disable counter/timer B7 from generating an interrupt based on COMPR1.
EN = 0x1 - Enable counter/timer B7 to generate an interrupt based on COMPR1.
25 TMRB7IE0 RW Counter/Timer B7 Interrupt Enable bit for COMPR0.

DIS = 0x0 - Disable counter/timer B7 from generating an interrupt based on COMPR0.
EN = 0x1 - Enable counter/timer B7 to generate an interrupt based on COMPR0
24:22 TMRB7FN RW Counter/Timer B7 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B7, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B7, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B7, assert, count to CMPR1B7, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B7, assert, count to CMPR1B7, deassert, restart.
SINGLEPATTERN = 0x4 - Single pattern.
REPEATPATTERN = 0x5 - Repeated pattern.
CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously.
ALTPWN = 0x7 - Alternate PWM
21:17 TMRB7CLK RW Counter/Timer B7 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINB.
HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4
HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV128 = 0x9 - Clock source is XT / 128
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)
XT_DIV4 = 0x10 - Clock source is XT / 4
XT_DIV8 = 0x11 - Clock source is XT / 8
XT_DIV32 = 0x12 - Clock source is XT / 32
RSVD = 0x13 - Clock source is Reserved.
CTMRA7 = 0x14 - Clock source is CTIMERA7 OUT.
CTMRA2 = 0x15 - Clock source is CTIMERA2 OUT.
CTMRB2 = 0x16 - Clock source is CTIMERB2 OUT.
CTMRA0 = 0x17 - Clock source is CTIMERA0 OUT.
CTMRB0 = 0x18 - Clock source is CTIMERB0 OUT.
CTMRB1 = 0x19 - Clock source is CTIMERB1 OUT.
CTMRB3 = 0x1A - Clock source is CTIMERB3 OUT.
CTMRB4 = 0x1B - Clock source is CTIMERB4 OUT.
CTMRB5 = 0x1C - Clock source is CTIMERB5 OUT.
BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses.
BUCKB = 0x1E - Clock source is Memory buck converter TON pulses.
BUCKA = 0x1F - Clock source is CPU buck converter TON pulses.
16 TMRB7EN RW Counter/Timer B7 Enable bit.

DIS = 0x0 - Counter/Timer B7 Disable.
EN = 0x1 - Counter/Timer B7 Enable.
15:13 RSVD RO RESERVED

12 TMRA7POL RW Counter/Timer A7 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINA7 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINA7 pin is the inverse of the timer output.
11 TMRA7CLR RW Counter/Timer A7 Clear bit.

RUN = 0x0 - Allow counter/timer A7 to run
CLEAR = 0x1 - Holds counter/timer A7 at 0x0000.
10 TMRA7IE1 RW Counter/Timer A7 Interrupt Enable bit based on COMPR1.

DIS = 0x0 - Disable counter/timer A7 from generating an interrupt based on COMPR1.
EN = 0x1 - Enable counter/timer A7 to generate an interrupt based on COMPR1.
9 TMRA7IE0 RW Counter/Timer A7 Interrupt Enable bit based on COMPR0.

DIS = 0x0 - Disable counter/timer A7 from generating an interrupt based on COMPR0.
EN = 0x1 - Enable counter/timer A7 to generate an interrupt based on COMPR0.
8:6 TMRA7FN RW Counter/Timer A7 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A7, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A7, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A7, assert, count to CMPR1A7, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A7, assert, count to CMPR1A7, deassert, restart.
SINGLEPATTERN = 0x4 - Single pattern.
REPEATPATTERN = 0x5 - Repeated pattern.
CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously.
ALTPWN = 0x7 - Alternate PWM
5:1 TMRA7CLK RW Counter/Timer A7 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINA.
HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4
HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV128 = 0x9 - Clock source is XT / 128
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)
XT_DIV4 = 0x10 - Clock source is XT / 4
XT_DIV8 = 0x11 - Clock source is XT / 8
XT_DIV32 = 0x12 - Clock source is XT / 32
RSVD = 0x13 - Clock source is Reserved.
CTMRB7 = 0x14 - Clock source is CTIMERB7 OUT.
CTMRA2 = 0x15 - Clock source is CTIMERA2 OUT.
CTMRB2 = 0x16 - Clock source is CTIMERB2 OUT.
CTMRA0 = 0x17 - Clock source is CTIMERA0 OUT.
CTMRB0 = 0x18 - Clock source is CTIMERB0 OUT.
CTMRB1 = 0x19 - Clock source is CTIMERB1 OUT.
CTMRB3 = 0x1A - Clock source is CTIMERB3 OUT.
CTMRB4 = 0x1B - Clock source is CTIMERB4 OUT.
CTMRB5 = 0x1C - Clock source is CTIMERB5 OUT.
BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses.
BUCKB = 0x1E - Clock source is Memory buck converter TON pulses.
BUCKA = 0x1F - Clock source is CPU buck converter TON pulses.
0 TMRA7EN RW Counter/Timer A7 Enable bit.

DIS = 0x0 - Counter/Timer A7 Disable.
EN = 0x1 - Counter/Timer A7 Enable.

CMPRAUXA7 - Counter/Timer A7 Compare Registers

Address:

  Instance 0 Address:   0x400080F4

Description:

Enhanced compare limits for timer half A.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR3A7
0x0
CMPR2A7
0x0

Bits Name RW Description
31:16 CMPR3A7 RW Counter/Timer A7 Compare Register 3. Holds the upper limit for timer half A.

15:0 CMPR2A7 RW Counter/Timer A7 Compare Register 2. Holds the lower limit for timer half A.


CMPRAUXB7 - Counter/Timer B7 Compare Registers

Address:

  Instance 0 Address:   0x400080F8

Description:

Enhanced compare limits for timer half B.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR3B7
0x0
CMPR2B7
0x0

Bits Name RW Description
31:16 CMPR3B7 RW Counter/Timer B7 Compare Register 3. Holds the upper limit for timer half B.

15:0 CMPR2B7 RW Counter/Timer B7 Compare Register 2. Holds the lower limit for timer half B.


AUX7 - Counter/Timer Auxiliary

Address:

  Instance 0 Address:   0x400080FC

Description:

Control bit fields for both halves of timer 0.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
TMRB7EN23
0x0
TMRB7POL23
0x0
TMRB7TINV
0x0
TMRB7NOSYNC
0x0
TMRB7TRIG
0x0
RSVD
0x0
TMRB7LMT
0x0
RSVD
0x0
TMRA7EN23
0x0
TMRA7POL23
0x0
TMRA7TINV
0x0
TMRA7NOSYNC
0x0
TMRA7TRIG
0x0
TMRA7LMT
0x0

Bits Name RW Description
31 RSVD RO RESERVED

30 TMRB7EN23 RW Counter/Timer B7 Upper compare enable.

DIS = 0x1 - Disable enhanced functions.
EN = 0x0 - Enable enhanced functions.
29 TMRB7POL23 RW Upper output polarity

NORM = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
28 TMRB7TINV RW Counter/Timer B7 Invert on trigger.

DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger
27 TMRB7NOSYNC RW Source clock synchronization control.

DIS = 0x0 - Synchronization on source clock
NOSYNC = 0x1 - No synchronization on source clock
26:23 TMRB7TRIG RW Counter/Timer B7 Trigger Select.

DIS = 0x0 - Trigger source is disabled.
A7OUT = 0x1 - Trigger source is CTIMERA7 OUT.
B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
A3OUT = 0x3 - Trigger source is CTIMERA3 OUT.
A5OUT = 0x4 - Trigger source is CTIMERA5 OUT.
B5OUT = 0x5 - Trigger source is CTIMERB5 OUT.
A2OUT = 0x6 - Trigger source is CTIMERA2 OUT.
B2OUT = 0x7 - Trigger source is CTIMERB2 OUT.
B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2.
A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2.
A2OUT2 = 0xA - Trigger source is CTIMERA2 OUT2.
B2OUT2 = 0xB - Trigger source is CTIMERB2 OUT2.
A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.
A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.
B1OUT2DUAL = 0xE - Trigger source is CTIMERB1 OUT2, dual edge.
A1OUT2DUAL = 0xF - Trigger source is CTIMERA1 OUT2, dual edge.
22 RSVD RO RESERVED

21:16 TMRB7LMT RW Counter/Timer B7 Pattern Limit Count.

15 RSVD RO RESERVED

14 TMRA7EN23 RW Counter/Timer A7 Upper compare enable.

DIS = 0x1 - Disable enhanced functions.
EN = 0x0 - Enable enhanced functions.
13 TMRA7POL23 RW Counter/Timer A7 Upper output polarity

NORM = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
12 TMRA7TINV RW Counter/Timer A7 Invert on trigger.

DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger
11 TMRA7NOSYNC RW Source clock synchronization control.

DIS = 0x0 - Synchronization on source clock
NOSYNC = 0x1 - No synchronization on source clock
10:7 TMRA7TRIG RW Counter/Timer A7 Trigger Select.

DIS = 0x0 - Trigger source is disabled.
B7OUT = 0x1 - Trigger source is CTIMERB7 OUT.
B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
A3OUT = 0x3 - Trigger source is CTIMERA3 OUT.
A1OUT = 0x4 - Trigger source is CTIMERA1 OUT.
B1OUT = 0x5 - Trigger source is CTIMERB1 OUT.
A4OUT = 0x6 - Trigger source is CTIMERA4 OUT.
B4OUT = 0x7 - Trigger source is CTIMERB4 OUT.
B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2.
A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2.
A2OUT2 = 0xA - Trigger source is CTIMERA2 OUT2.
B2OUT2 = 0xB - Trigger source is CTIMERB2 OUT2.
A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.
A5OUT2DUAL = 0xD - Trigger source is CTIMERA5 OUT2, dual edge.
B4OUT2DUAL = 0xE - Trigger source is CTIMERB4 OUT2, dual edge.
A4OUT2DUAL = 0xF - Trigger source is CTIMERA4 OUT2, dual edge.
6:0 TMRA7LMT RW Counter/Timer A7 Pattern Limit Count.


GLOBEN - Counter/Timer Global Enable

Address:

  Instance 0 Address:   0x40008100

Description:

Alternate enables for all CTIMERs.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ENB7
0x1
ENA7
0x1
ENB6
0x1
ENA6
0x1
ENB5
0x1
ENA5
0x1
ENB4
0x1
ENA4
0x1
ENB3
0x1
ENA3
0x1
ENB2
0x1
ENA2
0x1
ENB1
0x1
ENA1
0x1
ENB0
0x1
ENA0
0x1

Bits Name RW Description
31:16 RSVD RO RESERVED

15 ENB7 RW Alternate enable for B7.

LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
14 ENA7 RW Alternate enable for A7

LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
13 ENB6 RW Alternate enable for B6

LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
12 ENA6 RW Alternate enable for A6

LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
11 ENB5 RW Alternate enable for B5

LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
10 ENA5 RW Alternate enable for A5

LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
9 ENB4 RW Alternate enable for B4

LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
8 ENA4 RW Alternate enable for A4

LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
7 ENB3 RW Alternate enable for B3.

LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
6 ENA3 RW Alternate enable for A3

LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
5 ENB2 RW Alternate enable for B2

LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
4 ENA2 RW Alternate enable for A2

LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
3 ENB1 RW Alternate enable for B1

LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
2 ENA1 RW Alternate enable for A1

LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
1 ENB0 RW Alternate enable for B0

LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
0 ENA0 RW Alternate enable for A0

LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.

OUTCFG0 - Counter/Timer Output Config 0

Address:

  Instance 0 Address:   0x40008104

Description:

Pad output configuration 0.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CFG9
0x2
CFG8
0x2
CFG7
0x2
CFG6
0x2
CFG5
0x2
RSVD
0x0
CFG4
0x2
CFG3
0x1
CFG2
0x2
CFG1
0x2
CFG0
0x2

Bits Name RW Description
31 RSVD RO RESERVED

30:28 CFG9 RW Pad output 9 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
B0OUT = 0x5 - Output is B0OUT.
A4OUT = 0x4 - Output is A4OUT.
A2OUT = 0x3 - Output is A2OUT.
A2OUT2 = 0x2 - Output is A2OUT2
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
27:25 CFG8 RW Pad output 8 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
B6OUT = 0x5 - Output is B6OUT.
A4OUT2 = 0x4 - Output is A4OUT2.
A3OUT2 = 0x3 - Output is A3OUT.
A2OUT = 0x2 - Output is A2OUT
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
24:22 CFG7 RW Pad output 7 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
A7OUT = 0x5 - Output is A7OUT.
B5OUT = 0x4 - Output is B5OUT.
B1OUT = 0x3 - Output is B1OUT.
B1OUT2 = 0x2 - Output is B1OUT2
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
21:19 CFG6 RW Pad output 6 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
B7OUT = 0x5 - Output is B7OUT.
B5OUT2 = 0x4 - Output is B5OUT2.
A1OUT = 0x3 - Output is A1OUT.
B1OUT = 0x2 - Output is B1OUT
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
18:16 CFG5 RW Pad output 5 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
A7OUT = 0x5 - Output is A7OUT.
B6OUT = 0x4 - Output is A5OUT.
A1OUT = 0x3 - Output is A1OUT.
A1OUT2 = 0x2 - Output is A1OUT2
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
15 RSVD RO RESERVED

14:12 CFG4 RW Pad output 4 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
B5OUT = 0x5 - Output is B5OUT.
A5OUT2 = 0x4 - Output is A5OUT2.
A2OUT2 = 0x3 - Output is A2OUT2.
A1OUT = 0x2 - Output is A1OUT
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
11:9 CFG3 RW Pad output 3 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
A6OUT = 0x5 - Output is A6OUT.
A1OUT = 0x4 - Output is A1OUT.
B0OUT = 0x3 - Output is B0OUT.
B0OUT2 = 0x2 - Output is B0OUT2
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
8:6 CFG2 RW Pad output 2 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
A7OUT = 0x5 - Output is A7OUT.
B6OUT2 = 0x4 - Output is B6OUT2.
B1OUT2 = 0x3 - Output is B1OUT2.
B0OUT = 0x2 - Output is B0OUT
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
5:3 CFG1 RW Pad output 1 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
B7OUT2 = 0x5 - Output is B7OUT2.
A5OUT = 0x4 - Output is A5OUT.
A0OUT = 0x3 - Output is A0OUT.
A0OUT2 = 0x2 - Output is A0OUT2
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
2:0 CFG0 RW Pad output 0 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
A6OUT = 0x5 - Output is A6OUT.
A5OUT2 = 0x4 - Output is A5OUT2.
B2OUT2 = 0x3 - Output is B2OUT2.
A0OUT = 0x2 - Output is A0OUT
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0

OUTCFG1 - Counter/Timer Output Config 1

Address:

  Instance 0 Address:   0x40008108

Description:

Pad output configuration 1.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CFG19
0x2
CFG18
0x2
CFG17
0x2
CFG16
0x2
CFG15
0x2
RSVD
0x0
CFG14
0x2
CFG13
0x1
CFG12
0x2
CFG11
0x2
CFG10
0x2

Bits Name RW Description
31 RSVD RO RESERVED

30:28 CFG19 RW Pad output 19 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
B1OUT2 = 0x5 - Output is B1OUT2.
B4OUT = 0x4 - Output is B4OUT.
A2OUT = 0x3 - Output is A2OUT.
B4OUT2 = 0x2 - Output is B4OUT2
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
27:25 CFG18 RW Pad output 18 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
A3OUT2 = 0x5 - Output is A3OUT2.
A0OUT = 0x4 - Output is A0OUT.
B0OUT = 0x3 - Output is B0OUT.
B4OUT = 0x2 - Output is B4OUT
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
24:22 CFG17 RW Pad output 17 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
A1OUT2 = 0x5 - Output is A1OUT2.
A4OUT = 0x4 - Output is A4OUT.
B7OUT = 0x3 - Output is B7OUT.
A4OUT2 = 0x2 - Output is A4OUT2
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
21:19 CFG16 RW Pad output 16 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
B3OUT2 = 0x5 - Output is B3OUT2.
A0OUT2 = 0x4 - Output is A0OUT2.
A0OUT = 0x3 - Output is A0OUT.
A4OUT = 0x2 - Output is A4OUT
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
18:16 CFG15 RW Pad output 15 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
A4OUT2 = 0x5 - Output is A4OUT2.
A7OUT = 0x4 - Output is A7OUT.
B3OUT = 0x3 - Output is B3OUT.
B3OUT2 = 0x2 - Output is B3OUT2
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
15 RSVD RO RESERVED

14:12 CFG14 RW Pad output 14 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
A7OUT = 0x5 - Output is A7OUT.
B7OUT2 = 0x4 - Output is B7OUT2.
B1OUT = 0x3 - Output is B1OUT.
B3OUT = 0x2 - Output is B3OUT
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
11:9 CFG13 RW Pad output 13 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
B4OUT2 = 0x5 - Output is B4OUT2.
A6OUT = 0x4 - Output is A6OUT.
A3OUT = 0x3 - Output is A3OUT.
A3OUT2 = 0x2 - Output is A3OUT2
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
8:6 CFG12 RW Pad output 12 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
B6OUT2 = 0x5 - Output is B6OUT2.
B0OUT2 = 0x4 - Output is B0OUT2.
B1OUT = 0x3 - Output is B1OUT.
A3OUT = 0x2 - Output is A3OUT
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
5:3 CFG11 RW Pad output 11 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
B5OUT2 = 0x5 - Output is B5OUT2.
B4OUT = 0x4 - Output is B4OUT.
B2OUT = 0x3 - Output is B2OUT.
B2OUT2 = 0x2 - Output is B2OUT2
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
2:0 CFG10 RW Pad output 10 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
A6OUT = 0x5 - Output is A6OUT.
B4OUT2 = 0x4 - Output is B4OUT2.
B3OUT2 = 0x3 - Output is B3OUT2.
B2OUT = 0x2 - Output is B2OUT
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0

OUTCFG2 - Counter/Timer Output Config 2

Address:

  Instance 0 Address:   0x4000810C

Description:

Pad output configuration 2.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CFG29
0x2
CFG28
0x2
CFG27
0x2
CFG26
0x2
CFG25
0x2
RSVD
0x0
CFG24
0x2
CFG23
0x1
CFG22
0x2
CFG21
0x2
CFG20
0x2

Bits Name RW Description
31 RSVD RO RESERVED

30:28 CFG29 RW Pad output 29 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
A3OUT2 = 0x5 - Output is A3OUT2.
A7OUT = 0x4 - Output is A7OUT.
A1OUT = 0x3 - Output is A1OUT.
B5OUT2 = 0x2 - Output is B5OUT2
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
27:25 CFG28 RW Pad output 28 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
B0OUT2 = 0x5 - Output is B0OUT2.
A5OUT2 = 0x4 - Output is A5OUT2.
A3OUT = 0x3 - Output is A3OUT.
A7OUT = 0x2 - Output is A7OUT
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
24:22 CFG27 RW Pad output 27 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
B2OUT2 = 0x5 - Output is B2OUT2.
B6OUT = 0x4 - Output is B6OUT.
A1OUT = 0x3 - Output is A1OUT.
B6OUT2 = 0x2 - Output is B6OUT2
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
21:19 CFG26 RW Pad output 26 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
A1OUT2 = 0x5 - Output is A1OUT2.
A5OUT = 0x4 - Output is A5OUT.
B2OUT = 0x3 - Output is B2OUT.
B6OUT = 0x2 - Output is B6OUT
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
18:16 CFG25 RW Pad output 25 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
A2OUT2 = 0x5 - Output is A2OUT2.
A6OUT = 0x4 - Output is A6OUT.
B2OUT = 0x3 - Output is B2OUT.
B4OUT2 = 0x2 - Output is B4OUT2
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
15 RSVD RO RESERVED

14:12 CFG24 RW Pad output 24 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
B1OUT2 = 0x5 - Output is B1OUT2.
A1OUT = 0x4 - Output is A1OUT.
A2OUT = 0x3 - Output is A2OUT.
A6OUT = 0x2 - Output is A6OUT
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
11:9 CFG23 RW Pad output 23 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
B0OUT2 = 0x5 - Output is B0OUT2.
A5OUT = 0x4 - Output is A5OUT.
A7OUT = 0x3 - Output is A7OUT.
B5OUT2 = 0x2 - Output is B5OUT2
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
8:6 CFG22 RW Pad output 22 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
A2OUT2 = 0x5 - Output is A2OUT2.
A1OUT = 0x4 - Output is A1OUT.
A6OUT = 0x3 - Output is A6OUT.
B5OUT = 0x2 - Output is B5OUT
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
5:3 CFG21 RW Pad output 21 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
A0OUT2 = 0x5 - Output is A0OUT2.
B5OUT = 0x4 - Output is B5OUT.
A1OUT = 0x3 - Output is A1OUT.
A5OUT2 = 0x2 - Output is A5OUT2
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
2:0 CFG20 RW Pad output 20 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
B2OUT2 = 0x5 - Output is B2OUT2.
A1OUT2 = 0x4 - Output is A1OUT2.
A1OUT = 0x3 - Output is A1OUT.
A5OUT = 0x2 - Output is A5OUT
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0

OUTCFG3 - Counter/Timer Output Config 3

Address:

  Instance 0 Address:   0x40008114

Description:

Pad output configuration 3.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CFG31
0x2
CFG30
0x2

Bits Name RW Description
31:6 RSVD RO RESERVED

5:3 CFG31 RW Pad output 31 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
B3OUT2 = 0x5 - Output is B3OUT2.
B7OUT = 0x4 - Output is B7OUT.
A6OUT = 0x3 - Output is A6OUT.
B7OUT2 = 0x2 - Output is B7OUT2
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0
2:0 CFG30 RW Pad output 30 configuration

A7OUT2 = 0x7 - Output is A7OUT2.
A6OUT2 = 0x6 - Output is A6OUT2.
A0OUT2 = 0x5 - Output is A0OUT2.
A4OUT2 = 0x4 - Output is A4OUT2.
B3OUT = 0x3 - Output is B3OUT.
B7OUT = 0x2 - Output is B7OUT
ONE = 0x1 - Force output to 1.
ZERO = 0x0 - Force output to 0

INCFG - Counter/Timer Input Config

Address:

  Instance 0 Address:   0x40008118

Description:

Pad input configuration.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CFGB7
0x0
CFGA7
0x0
CFGB6
0x0
CFGA6
0x0
CFGB5
0x0
CFGA5
0x0
CFGB4
0x0
CFGA4
0x0
CFGB3
0x0
CFGA3
0x0
CFGB2
0x0
CFGA2
0x0
CFGB1
0x0
CFGA1
0x0
CFGB0
0x0
CFGA0
0x0

Bits Name RW Description
31:16 RSVD RO RESERVED

15 CFGB7 RW CTIMER B7 input configuration

CT31 = 0x1 - Input is CT31
CT30 = 0x0 - Input is CT30
14 CFGA7 RW CTIMER A7 input configuration

CT29 = 0x1 - Input is CT29
CT28 = 0x0 - Input is CT28
13 CFGB6 RW CTIMER B6 input configuration

CT27 = 0x1 - Input is CT27
CT26 = 0x0 - Input is CT26
12 CFGA6 RW CTIMER A6 input configuration

CT25 = 0x1 - Input is CT25
CT24 = 0x0 - Input is CT24
11 CFGB5 RW CTIMER B5 input configuration

CT23 = 0x1 - Input is CT23
CT22 = 0x0 - Input is CT22
10 CFGA5 RW CTIMER A5 input configuration

CT21 = 0x1 - Input is CT21
CT20 = 0x0 - Input is CT20
9 CFGB4 RW CTIMER B4 input configuration

CT19 = 0x1 - Input is CT19
CT18 = 0x0 - Input is CT18
8 CFGA4 RW CTIMER A4 input configuration

CT17 = 0x1 - Input is CT17
CT16 = 0x0 - Input is CT16
7 CFGB3 RW CTIMER B3 input configuration

CT15 = 0x1 - Input is CT15
CT14 = 0x0 - Input is CT14
6 CFGA3 RW CTIMER A3 input configuration

CT13 = 0x1 - Input is CT13
CT12 = 0x0 - Input is CT12
5 CFGB2 RW CTIMER B2 input configuration

CT11 = 0x1 - Input is CT11
CT10 = 0x0 - Input is CT10
4 CFGA2 RW CTIMER A2 input configuration

CT9 = 0x1 - Input is CT9
CT8 = 0x0 - Input is CT8
3 CFGB1 RW CTIMER B1 input configuration

CT7 = 0x1 - Input is CT7
CT6 = 0x0 - Input is CT6
2 CFGA1 RW CTIMER A1 input configuration

CT5 = 0x1 - Input is CT5
CT4 = 0x0 - Input is CT4
1 CFGB0 RW CTIMER B0 input configuration

CT3 = 0x1 - Input is CT3
CT2 = 0x0 - Input is CT2
0 CFGA0 RW CTIMER A0 input configuration

CT1 = 0x1 - Input is CT1
CT0 = 0x0 - Input is CT0

STCFG - Configuration Register

Address:

  Instance 0 Address:   0x40008140

Description:

The STIMER Configuration Register contains the software control for selecting the clock divider and source feeding the system timer.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FREEZE
0x1
CLEAR
0x0
RSVD
0x0
COMPARE_H_EN
0x0
COMPARE_G_EN
0x0
COMPARE_F_EN
0x0
COMPARE_E_EN
0x0
COMPARE_D_EN
0x0
COMPARE_C_EN
0x0
COMPARE_B_EN
0x0
COMPARE_A_EN
0x0
RSVD
0x0
CLKSEL
0x0

Bits Name RW Description
31 FREEZE RW Set this bit to one to freeze the clock input to the COUNTER register. Once frozen, the value can be safely written from the MCU. Unfreeze to resume.

THAW = 0x0 - Let the COUNTER register run on its input clock.
FREEZE = 0x1 - Stop the COUNTER register for loading.
30 CLEAR RW Set this bit to one to clear the System Timer register. If this bit is set to '1', the system timer register will stay cleared. It needs to be set to '0' for the system timer to start running.

RUN = 0x0 - Let the COUNTER register run on its input clock.
CLEAR = 0x1 - Stop the COUNTER register for loading.
29:16 RSVD RO RESERVED.

15 COMPARE_H_EN RW Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.

DISABLE = 0x0 - Compare H disabled.
ENABLE = 0x1 - Compare H enabled.
14 COMPARE_G_EN RW Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.

DISABLE = 0x0 - Compare G disabled.
ENABLE = 0x1 - Compare G enabled.
13 COMPARE_F_EN RW Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.

DISABLE = 0x0 - Compare F disabled.
ENABLE = 0x1 - Compare F enabled.
12 COMPARE_E_EN RW Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.

DISABLE = 0x0 - Compare E disabled.
ENABLE = 0x1 - Compare E enabled.
11 COMPARE_D_EN RW Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.

DISABLE = 0x0 - Compare D disabled.
ENABLE = 0x1 - Compare D enabled.
10 COMPARE_C_EN RW Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.

DISABLE = 0x0 - Compare C disabled.
ENABLE = 0x1 - Compare C enabled.
9 COMPARE_B_EN RW Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.

DISABLE = 0x0 - Compare B disabled.
ENABLE = 0x1 - Compare B enabled.
8 COMPARE_A_EN RW Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.

DISABLE = 0x0 - Compare A disabled.
ENABLE = 0x1 - Compare A enabled.
7:4 RSVD RO RESERVED.

3:0 CLKSEL RW Selects an appropriate clock source and divider to use for the System Timer clock.

NOCLK = 0x0 - No clock enabled.
HFRC_DIV16 = 0x1 - 3MHz from the HFRC clock divider.
HFRC_DIV256 = 0x2 - 187.5KHz from the HFRC clock divider.
XTAL_DIV1 = 0x3 - 32768Hz from the crystal oscillator.
XTAL_DIV2 = 0x4 - 16384Hz from the crystal oscillator.
XTAL_DIV32 = 0x5 - 1024Hz from the crystal oscillator.
LFRC_DIV1 = 0x6 - Approximately 1KHz from the LFRC oscillator (uncalibrated).
CTIMER0A = 0x7 - Use CTIMER 0 section A as a prescaler for the clock source.
CTIMER0B = 0x8 - Use CTIMER 0 section B (or A and B linked together) as a prescaler for the clock source.

STTMR - System Timer Count Register (Real Time Counter)

Address:

  Instance 0 Address:   0x40008144

Description:

The COUNTER Register contains the running count of time as maintained by incrementing for every rising clock edge of the clock source selected in the configuration register. It is this counter value that captured in the capture registers and it is this counter value that is compared against the various compare registers. This register cannot be written, but can be cleared to 0 for a deterministic value. Use the FREEZE bit will stop this counter from incrementing.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STTMR
0x0

Bits Name RW Description
31:0 STTMR RO Value of the 32-bit counter as it ticks over.


CAPTURECONTROL - Capture Control Register

Address:

  Instance 0 Address:   0x40008148

Description:

The STIMER Capture Control Register controls each of the 4 capture registers. It selects their GPIO pin number for a trigger source, enables a capture operation and sets the input polarity for the capture. NOTE: 8-bit writes can control individual capture registers atomically.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CAPTURE3
0x0
CAPTURE2
0x0
CAPTURE1
0x0
CAPTURE0
0x0

Bits Name RW Description
31:4 RSVD RO RESERVED.

3 CAPTURE3 RW Selects whether capture is enabled for the specified capture register.

DISABLE = 0x0 - Capture function disabled.
ENABLE = 0x1 - Capture function enabled.
2 CAPTURE2 RW Selects whether capture is enabled for the specified capture register.

DISABLE = 0x0 - Capture function disabled.
ENABLE = 0x1 - Capture function enabled.
1 CAPTURE1 RW Selects whether capture is enabled for the specified capture register.

DISABLE = 0x0 - Capture function disabled.
ENABLE = 0x1 - Capture function enabled.
0 CAPTURE0 RW Selects whether capture is enabled for the specified capture register.

DISABLE = 0x0 - Capture function disabled.
ENABLE = 0x1 - Capture function enabled.

SCMPR0 - Compare Register A

Address:

  Instance 0 Address:   0x40008150

Description:

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCMPR0
0x0

Bits Name RW Description
31:0 SCMPR0 RW Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCGF register.


SCMPR1 - Compare Register B

Address:

  Instance 0 Address:   0x40008154

Description:

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCMPR1
0x0

Bits Name RW Description
31:0 SCMPR1 RW Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_B_EN bit in the REG_CTIMER_STCGF register.


SCMPR2 - Compare Register C

Address:

  Instance 0 Address:   0x40008158

Description:

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCMPR2
0x0

Bits Name RW Description
31:0 SCMPR2 RW Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_C_EN bit in the REG_CTIMER_STCGF register.


SCMPR3 - Compare Register D

Address:

  Instance 0 Address:   0x4000815C

Description:

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCMPR3
0x0

Bits Name RW Description
31:0 SCMPR3 RW Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_D_EN bit in the REG_CTIMER_STCGF register.


SCMPR4 - Compare Register E

Address:

  Instance 0 Address:   0x40008160

Description:

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCMPR4
0x0

Bits Name RW Description
31:0 SCMPR4 RW Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_E_EN bit in the REG_CTIMER_STCGF register.


SCMPR5 - Compare Register F

Address:

  Instance 0 Address:   0x40008164

Description:

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCMPR5
0x0

Bits Name RW Description
31:0 SCMPR5 RW Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_F_EN bit in the REG_CTIMER_STCGF register.


SCMPR6 - Compare Register G

Address:

  Instance 0 Address:   0x40008168

Description:

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCMPR6
0x0

Bits Name RW Description
31:0 SCMPR6 RW Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_G_EN bit in the REG_CTIMER_STCGF register.


SCMPR7 - Compare Register H

Address:

  Instance 0 Address:   0x4000816C

Description:

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCMPR7
0x0

Bits Name RW Description
31:0 SCMPR7 RW Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_H_EN bit in the REG_CTIMER_STCGF register.


SCAPT0 - Capture Register A

Address:

  Instance 0 Address:   0x400081E0

Description:

The STIMER capture Register A grabs the VALUE in the COUNTER register whenever capture condition (event) A is asserted. This register holds a time stamp for the event.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCAPT0
0x0

Bits Name RW Description
31:0 SCAPT0 RO Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.


SCAPT1 - Capture Register B

Address:

  Instance 0 Address:   0x400081E4

Description:

The STIMER capture Register B grabs the VALUE in the COUNTER register whenever capture condition (event) B is asserted. This register holds a time stamp for the event.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCAPT1
0x0

Bits Name RW Description
31:0 SCAPT1 RO Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.


SCAPT2 - Capture Register C

Address:

  Instance 0 Address:   0x400081E8

Description:

The STIMER capture Register C grabs the VALUE in the COUNTER register whenever capture condition (event) C is asserted. This register holds a time stamp for the event.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCAPT2
0x0

Bits Name RW Description
31:0 SCAPT2 RO Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.


SCAPT3 - Capture Register D

Address:

  Instance 0 Address:   0x400081EC

Description:

The STIMER capture Register D grabs the VALUE in the COUNTER register whenever capture condition (event) D is asserted. This register holds a time stamp for the event.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCAPT3
0x0

Bits Name RW Description
31:0 SCAPT3 RO Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.


SNVR0 - System Timer NVRAM_A Register

Address:

  Instance 0 Address:   0x400081F0

Description:

The NVRAM_A Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power cycles.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SNVR0
0x0

Bits Name RW Description
31:0 SNVR0 RW Value of the 32-bit counter as it ticks over.


SNVR1 - System Timer NVRAM_B Register

Address:

  Instance 0 Address:   0x400081F4

Description:

The NVRAM_B Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power cycles.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SNVR1
0x0

Bits Name RW Description
31:0 SNVR1 RW Value of the 32-bit counter as it ticks over.


SNVR2 - System Timer NVRAM_C Register

Address:

  Instance 0 Address:   0x400081F8

Description:

The NVRAM_C Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power cycles.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SNVR2
0x0

Bits Name RW Description
31:0 SNVR2 RW Value of the 32-bit counter as it ticks over.


SNVR3 - System Timer NVRAM_D Register

Address:

  Instance 0 Address:   0x400081FC

Description:

The NVRAM_D Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power cycles.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SNVR3
0x0

Bits Name RW Description
31:0 SNVR3 RW Value of the 32-bit counter as it ticks over.


INTEN - Counter/Timer Interrupts: Enable

Address:

  Instance 0 Address:   0x40008200

Description:

Set bits in this register to allow this module to generate the corresponding interrupt.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTMRB7C1INT
0x0
CTMRA7C1INT
0x0
CTMRB6C1INT
0x0
CTMRA6C1INT
0x0
CTMRB5C1INT
0x0
CTMRA5C1INT
0x0
CTMRB4C1INT
0x0
CTMRA4C1INT
0x0
CTMRB3C1INT
0x0
CTMRA3C1INT
0x0
CTMRB2C1INT
0x0
CTMRA2C1INT
0x0
CTMRB1C1INT
0x0
CTMRA1C1INT
0x0
CTMRB0C1INT
0x0
CTMRA0C1INT
0x0
CTMRB7C0INT
0x0
CTMRA7C0INT
0x0
CTMRB6C0INT
0x0
CTMRA6C0INT
0x0
CTMRB5C0INT
0x0
CTMRA5C0INT
0x0
CTMRB4C0INT
0x0
CTMRA4C0INT
0x0
CTMRB3C0INT
0x0
CTMRA3C0INT
0x0
CTMRB2C0INT
0x0
CTMRA2C0INT
0x0
CTMRB1C0INT
0x0
CTMRA1C0INT
0x0
CTMRB0C0INT
0x0
CTMRA0C0INT
0x0

Bits Name RW Description
31 CTMRB7C1INT RW Counter/Timer B7 interrupt based on COMPR1.

30 CTMRA7C1INT RW Counter/Timer A7 interrupt based on COMPR1.

29 CTMRB6C1INT RW Counter/Timer B6 interrupt based on COMPR1.

28 CTMRA6C1INT RW Counter/Timer A6 interrupt based on COMPR1.

27 CTMRB5C1INT RW Counter/Timer B5 interrupt based on COMPR1.

26 CTMRA5C1INT RW Counter/Timer A5 interrupt based on COMPR1.

25 CTMRB4C1INT RW Counter/Timer B4 interrupt based on COMPR1.

24 CTMRA4C1INT RW Counter/Timer A4 interrupt based on COMPR1.

23 CTMRB3C1INT RW Counter/Timer B3 interrupt based on COMPR1.

22 CTMRA3C1INT RW Counter/Timer A3 interrupt based on COMPR1.

21 CTMRB2C1INT RW Counter/Timer B2 interrupt based on COMPR1.

20 CTMRA2C1INT RW Counter/Timer A2 interrupt based on COMPR1.

19 CTMRB1C1INT RW Counter/Timer B1 interrupt based on COMPR1.

18 CTMRA1C1INT RW Counter/Timer A1 interrupt based on COMPR1.

17 CTMRB0C1INT RW Counter/Timer B0 interrupt based on COMPR1.

16 CTMRA0C1INT RW Counter/Timer A0 interrupt based on COMPR1.

15 CTMRB7C0INT RW Counter/Timer B7 interrupt based on COMPR0.

14 CTMRA7C0INT RW Counter/Timer A7 interrupt based on COMPR0.

13 CTMRB6C0INT RW Counter/Timer B6 interrupt based on COMPR0.

12 CTMRA6C0INT RW Counter/Timer A6 interrupt based on COMPR0.

11 CTMRB5C0INT RW Counter/Timer B5 interrupt based on COMPR0.

10 CTMRA5C0INT RW Counter/Timer A5 interrupt based on COMPR0.

9 CTMRB4C0INT RW Counter/Timer B4 interrupt based on COMPR0.

8 CTMRA4C0INT RW Counter/Timer A4 interrupt based on COMPR0.

7 CTMRB3C0INT RW Counter/Timer B3 interrupt based on COMPR0.

6 CTMRA3C0INT RW Counter/Timer A3 interrupt based on COMPR0.

5 CTMRB2C0INT RW Counter/Timer B2 interrupt based on COMPR0.

4 CTMRA2C0INT RW Counter/Timer A2 interrupt based on COMPR0.

3 CTMRB1C0INT RW Counter/Timer B1 interrupt based on COMPR0.

2 CTMRA1C0INT RW Counter/Timer A1 interrupt based on COMPR0.

1 CTMRB0C0INT RW Counter/Timer B0 interrupt based on COMPR0.

0 CTMRA0C0INT RW Counter/Timer A0 interrupt based on COMPR0.


INTSTAT - Counter/Timer Interrupts: Status

Address:

  Instance 0 Address:   0x40008204

Description:

Read bits from this register to discover the cause of a recent interrupt.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTMRB7C1INT
0x0
CTMRA7C1INT
0x0
CTMRB6C1INT
0x0
CTMRA6C1INT
0x0
CTMRB5C1INT
0x0
CTMRA5C1INT
0x0
CTMRB4C1INT
0x0
CTMRA4C1INT
0x0
CTMRB3C1INT
0x0
CTMRA3C1INT
0x0
CTMRB2C1INT
0x0
CTMRA2C1INT
0x0
CTMRB1C1INT
0x0
CTMRA1C1INT
0x0
CTMRB0C1INT
0x0
CTMRA0C1INT
0x0
CTMRB7C0INT
0x0
CTMRA7C0INT
0x0
CTMRB6C0INT
0x0
CTMRA6C0INT
0x0
CTMRB5C0INT
0x0
CTMRA5C0INT
0x0
CTMRB4C0INT
0x0
CTMRA4C0INT
0x0
CTMRB3C0INT
0x0
CTMRA3C0INT
0x0
CTMRB2C0INT
0x0
CTMRA2C0INT
0x0
CTMRB1C0INT
0x0
CTMRA1C0INT
0x0
CTMRB0C0INT
0x0
CTMRA0C0INT
0x0

Bits Name RW Description
31 CTMRB7C1INT RW Counter/Timer B7 interrupt based on COMPR1.

30 CTMRA7C1INT RW Counter/Timer A7 interrupt based on COMPR1.

29 CTMRB6C1INT RW Counter/Timer B6 interrupt based on COMPR1.

28 CTMRA6C1INT RW Counter/Timer A6 interrupt based on COMPR1.

27 CTMRB5C1INT RW Counter/Timer B5 interrupt based on COMPR1.

26 CTMRA5C1INT RW Counter/Timer A5 interrupt based on COMPR1.

25 CTMRB4C1INT RW Counter/Timer B4 interrupt based on COMPR1.

24 CTMRA4C1INT RW Counter/Timer A4 interrupt based on COMPR1.

23 CTMRB3C1INT RW Counter/Timer B3 interrupt based on COMPR1.

22 CTMRA3C1INT RW Counter/Timer A3 interrupt based on COMPR1.

21 CTMRB2C1INT RW Counter/Timer B2 interrupt based on COMPR1.

20 CTMRA2C1INT RW Counter/Timer A2 interrupt based on COMPR1.

19 CTMRB1C1INT RW Counter/Timer B1 interrupt based on COMPR1.

18 CTMRA1C1INT RW Counter/Timer A1 interrupt based on COMPR1.

17 CTMRB0C1INT RW Counter/Timer B0 interrupt based on COMPR1.

16 CTMRA0C1INT RW Counter/Timer A0 interrupt based on COMPR1.

15 CTMRB7C0INT RW Counter/Timer B7 interrupt based on COMPR0.

14 CTMRA7C0INT RW Counter/Timer A7 interrupt based on COMPR0.

13 CTMRB6C0INT RW Counter/Timer B6 interrupt based on COMPR0.

12 CTMRA6C0INT RW Counter/Timer A6 interrupt based on COMPR0.

11 CTMRB5C0INT RW Counter/Timer B5 interrupt based on COMPR0.

10 CTMRA5C0INT RW Counter/Timer A5 interrupt based on COMPR0.

9 CTMRB4C0INT RW Counter/Timer B4 interrupt based on COMPR0.

8 CTMRA4C0INT RW Counter/Timer A4 interrupt based on COMPR0.

7 CTMRB3C0INT RW Counter/Timer B3 interrupt based on COMPR0.

6 CTMRA3C0INT RW Counter/Timer A3 interrupt based on COMPR0.

5 CTMRB2C0INT RW Counter/Timer B2 interrupt based on COMPR0.

4 CTMRA2C0INT RW Counter/Timer A2 interrupt based on COMPR0.

3 CTMRB1C0INT RW Counter/Timer B1 interrupt based on COMPR0.

2 CTMRA1C0INT RW Counter/Timer A1 interrupt based on COMPR0.

1 CTMRB0C0INT RW Counter/Timer B0 interrupt based on COMPR0.

0 CTMRA0C0INT RW Counter/Timer A0 interrupt based on COMPR0.


INTCLR - Counter/Timer Interrupts: Clear

Address:

  Instance 0 Address:   0x40008208

Description:

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTMRB7C1INT
0x0
CTMRA7C1INT
0x0
CTMRB6C1INT
0x0
CTMRA6C1INT
0x0
CTMRB5C1INT
0x0
CTMRA5C1INT
0x0
CTMRB4C1INT
0x0
CTMRA4C1INT
0x0
CTMRB3C1INT
0x0
CTMRA3C1INT
0x0
CTMRB2C1INT
0x0
CTMRA2C1INT
0x0
CTMRB1C1INT
0x0
CTMRA1C1INT
0x0
CTMRB0C1INT
0x0
CTMRA0C1INT
0x0
CTMRB7C0INT
0x0
CTMRA7C0INT
0x0
CTMRB6C0INT
0x0
CTMRA6C0INT
0x0
CTMRB5C0INT
0x0
CTMRA5C0INT
0x0
CTMRB4C0INT
0x0
CTMRA4C0INT
0x0
CTMRB3C0INT
0x0
CTMRA3C0INT
0x0
CTMRB2C0INT
0x0
CTMRA2C0INT
0x0
CTMRB1C0INT
0x0
CTMRA1C0INT
0x0
CTMRB0C0INT
0x0
CTMRA0C0INT
0x0

Bits Name RW Description
31 CTMRB7C1INT RW Counter/Timer B7 interrupt based on COMPR1.

30 CTMRA7C1INT RW Counter/Timer A7 interrupt based on COMPR1.

29 CTMRB6C1INT RW Counter/Timer B6 interrupt based on COMPR1.

28 CTMRA6C1INT RW Counter/Timer A6 interrupt based on COMPR1.

27 CTMRB5C1INT RW Counter/Timer B5 interrupt based on COMPR1.

26 CTMRA5C1INT RW Counter/Timer A5 interrupt based on COMPR1.

25 CTMRB4C1INT RW Counter/Timer B4 interrupt based on COMPR1.

24 CTMRA4C1INT RW Counter/Timer A4 interrupt based on COMPR1.

23 CTMRB3C1INT RW Counter/Timer B3 interrupt based on COMPR1.

22 CTMRA3C1INT RW Counter/Timer A3 interrupt based on COMPR1.

21 CTMRB2C1INT RW Counter/Timer B2 interrupt based on COMPR1.

20 CTMRA2C1INT RW Counter/Timer A2 interrupt based on COMPR1.

19 CTMRB1C1INT RW Counter/Timer B1 interrupt based on COMPR1.

18 CTMRA1C1INT RW Counter/Timer A1 interrupt based on COMPR1.

17 CTMRB0C1INT RW Counter/Timer B0 interrupt based on COMPR1.

16 CTMRA0C1INT RW Counter/Timer A0 interrupt based on COMPR1.

15 CTMRB7C0INT RW Counter/Timer B7 interrupt based on COMPR0.

14 CTMRA7C0INT RW Counter/Timer A7 interrupt based on COMPR0.

13 CTMRB6C0INT RW Counter/Timer B6 interrupt based on COMPR0.

12 CTMRA6C0INT RW Counter/Timer A6 interrupt based on COMPR0.

11 CTMRB5C0INT RW Counter/Timer B5 interrupt based on COMPR0.

10 CTMRA5C0INT RW Counter/Timer A5 interrupt based on COMPR0.

9 CTMRB4C0INT RW Counter/Timer B4 interrupt based on COMPR0.

8 CTMRA4C0INT RW Counter/Timer A4 interrupt based on COMPR0.

7 CTMRB3C0INT RW Counter/Timer B3 interrupt based on COMPR0.

6 CTMRA3C0INT RW Counter/Timer A3 interrupt based on COMPR0.

5 CTMRB2C0INT RW Counter/Timer B2 interrupt based on COMPR0.

4 CTMRA2C0INT RW Counter/Timer A2 interrupt based on COMPR0.

3 CTMRB1C0INT RW Counter/Timer B1 interrupt based on COMPR0.

2 CTMRA1C0INT RW Counter/Timer A1 interrupt based on COMPR0.

1 CTMRB0C0INT RW Counter/Timer B0 interrupt based on COMPR0.

0 CTMRA0C0INT RW Counter/Timer A0 interrupt based on COMPR0.


INTSET - Counter/Timer Interrupts: Set

Address:

  Instance 0 Address:   0x4000820C

Description:

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTMRB7C1INT
0x0
CTMRA7C1INT
0x0
CTMRB6C1INT
0x0
CTMRA6C1INT
0x0
CTMRB5C1INT
0x0
CTMRA5C1INT
0x0
CTMRB4C1INT
0x0
CTMRA4C1INT
0x0
CTMRB3C1INT
0x0
CTMRA3C1INT
0x0
CTMRB2C1INT
0x0
CTMRA2C1INT
0x0
CTMRB1C1INT
0x0
CTMRA1C1INT
0x0
CTMRB0C1INT
0x0
CTMRA0C1INT
0x0
CTMRB7C0INT
0x0
CTMRA7C0INT
0x0
CTMRB6C0INT
0x0
CTMRA6C0INT
0x0
CTMRB5C0INT
0x0
CTMRA5C0INT
0x0
CTMRB4C0INT
0x0
CTMRA4C0INT
0x0
CTMRB3C0INT
0x0
CTMRA3C0INT
0x0
CTMRB2C0INT
0x0
CTMRA2C0INT
0x0
CTMRB1C0INT
0x0
CTMRA1C0INT
0x0
CTMRB0C0INT
0x0
CTMRA0C0INT
0x0

Bits Name RW Description
31 CTMRB7C1INT RW Counter/Timer B7 interrupt based on COMPR1.

30 CTMRA7C1INT RW Counter/Timer A7 interrupt based on COMPR1.

29 CTMRB6C1INT RW Counter/Timer B6 interrupt based on COMPR1.

28 CTMRA6C1INT RW Counter/Timer A6 interrupt based on COMPR1.

27 CTMRB5C1INT RW Counter/Timer B5 interrupt based on COMPR1.

26 CTMRA5C1INT RW Counter/Timer A5 interrupt based on COMPR1.

25 CTMRB4C1INT RW Counter/Timer B4 interrupt based on COMPR1.

24 CTMRA4C1INT RW Counter/Timer A4 interrupt based on COMPR1.

23 CTMRB3C1INT RW Counter/Timer B3 interrupt based on COMPR1.

22 CTMRA3C1INT RW Counter/Timer A3 interrupt based on COMPR1.

21 CTMRB2C1INT RW Counter/Timer B2 interrupt based on COMPR1.

20 CTMRA2C1INT RW Counter/Timer A2 interrupt based on COMPR1.

19 CTMRB1C1INT RW Counter/Timer B1 interrupt based on COMPR1.

18 CTMRA1C1INT RW Counter/Timer A1 interrupt based on COMPR1.

17 CTMRB0C1INT RW Counter/Timer B0 interrupt based on COMPR1.

16 CTMRA0C1INT RW Counter/Timer A0 interrupt based on COMPR1.

15 CTMRB7C0INT RW Counter/Timer B7 interrupt based on COMPR0.

14 CTMRA7C0INT RW Counter/Timer A7 interrupt based on COMPR0.

13 CTMRB6C0INT RW Counter/Timer B6 interrupt based on COMPR0.

12 CTMRA6C0INT RW Counter/Timer A6 interrupt based on COMPR0.

11 CTMRB5C0INT RW Counter/Timer B5 interrupt based on COMPR0.

10 CTMRA5C0INT RW Counter/Timer A5 interrupt based on COMPR0.

9 CTMRB4C0INT RW Counter/Timer B4 interrupt based on COMPR0.

8 CTMRA4C0INT RW Counter/Timer A4 interrupt based on COMPR0.

7 CTMRB3C0INT RW Counter/Timer B3 interrupt based on COMPR0.

6 CTMRA3C0INT RW Counter/Timer A3 interrupt based on COMPR0.

5 CTMRB2C0INT RW Counter/Timer B2 interrupt based on COMPR0.

4 CTMRA2C0INT RW Counter/Timer A2 interrupt based on COMPR0.

3 CTMRB1C0INT RW Counter/Timer B1 interrupt based on COMPR0.

2 CTMRA1C0INT RW Counter/Timer A1 interrupt based on COMPR0.

1 CTMRB0C0INT RW Counter/Timer B0 interrupt based on COMPR0.

0 CTMRA0C0INT RW Counter/Timer A0 interrupt based on COMPR0.


STMINTEN - STIMER Interrupt registers: Enable

Address:

  Instance 0 Address:   0x40008300

Description:

Set bits in this register to allow this module to generate the corresponding interrupt.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CAPTURED
0x0
CAPTUREC
0x0
CAPTUREB
0x0
CAPTUREA
0x0
OVERFLOW
0x0
COMPAREH
0x0
COMPAREG
0x0
COMPAREF
0x0
COMPAREE
0x0
COMPARED
0x0
COMPAREC
0x0
COMPAREB
0x0
COMPAREA
0x0

Bits Name RW Description
31:13 RSVD RO RESERVED.

12 CAPTURED RW CAPTURE register D has grabbed the value in the counter

CAPD_INT = 0x1 - Capture D interrupt status bit was set.
11 CAPTUREC RW CAPTURE register C has grabbed the value in the counter

CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set.
10 CAPTUREB RW CAPTURE register B has grabbed the value in the counter

CAPB_INT = 0x1 - CAPTURE B interrupt status bit was set.
9 CAPTUREA RW CAPTURE register A has grabbed the value in the counter

CAPA_INT = 0x1 - CAPTURE A interrupt status bit was set.
8 OVERFLOW RW COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.

OFLOW_INT = 0x1 - Overflow interrupt status bit was set.
7 COMPAREH RW COUNTER is greater than or equal to COMPARE register H.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
6 COMPAREG RW COUNTER is greater than or equal to COMPARE register G.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
5 COMPAREF RW COUNTER is greater than or equal to COMPARE register F.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
4 COMPAREE RW COUNTER is greater than or equal to COMPARE register E.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
3 COMPARED RW COUNTER is greater than or equal to COMPARE register D.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
2 COMPAREC RW COUNTER is greater than or equal to COMPARE register C.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
1 COMPAREB RW COUNTER is greater than or equal to COMPARE register B.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
0 COMPAREA RW COUNTER is greater than or equal to COMPARE register A.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.

STMINTSTAT - STIMER Interrupt registers: Status

Address:

  Instance 0 Address:   0x40008304

Description:

Read bits from this register to discover the cause of a recent interrupt.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CAPTURED
0x0
CAPTUREC
0x0
CAPTUREB
0x0
CAPTUREA
0x0
OVERFLOW
0x0
COMPAREH
0x0
COMPAREG
0x0
COMPAREF
0x0
COMPAREE
0x0
COMPARED
0x0
COMPAREC
0x0
COMPAREB
0x0
COMPAREA
0x0

Bits Name RW Description
31:13 RSVD RO RESERVED.

12 CAPTURED RW CAPTURE register D has grabbed the value in the counter

CAPD_INT = 0x1 - Capture D interrupt status bit was set.
11 CAPTUREC RW CAPTURE register C has grabbed the value in the counter

CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set.
10 CAPTUREB RW CAPTURE register B has grabbed the value in the counter

CAPB_INT = 0x1 - CAPTURE B interrupt status bit was set.
9 CAPTUREA RW CAPTURE register A has grabbed the value in the counter

CAPA_INT = 0x1 - CAPTURE A interrupt status bit was set.
8 OVERFLOW RW COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.

OFLOW_INT = 0x1 - Overflow interrupt status bit was set.
7 COMPAREH RW COUNTER is greater than or equal to COMPARE register H.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
6 COMPAREG RW COUNTER is greater than or equal to COMPARE register G.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
5 COMPAREF RW COUNTER is greater than or equal to COMPARE register F.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
4 COMPAREE RW COUNTER is greater than or equal to COMPARE register E.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
3 COMPARED RW COUNTER is greater than or equal to COMPARE register D.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
2 COMPAREC RW COUNTER is greater than or equal to COMPARE register C.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
1 COMPAREB RW COUNTER is greater than or equal to COMPARE register B.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
0 COMPAREA RW COUNTER is greater than or equal to COMPARE register A.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.

STMINTCLR - STIMER Interrupt registers: Clear

Address:

  Instance 0 Address:   0x40008308

Description:

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CAPTURED
0x0
CAPTUREC
0x0
CAPTUREB
0x0
CAPTUREA
0x0
OVERFLOW
0x0
COMPAREH
0x0
COMPAREG
0x0
COMPAREF
0x0
COMPAREE
0x0
COMPARED
0x0
COMPAREC
0x0
COMPAREB
0x0
COMPAREA
0x0

Bits Name RW Description
31:13 RSVD RO RESERVED.

12 CAPTURED RW CAPTURE register D has grabbed the value in the counter

CAPD_INT = 0x1 - Capture D interrupt status bit was set.
11 CAPTUREC RW CAPTURE register C has grabbed the value in the counter

CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set.
10 CAPTUREB RW CAPTURE register B has grabbed the value in the counter

CAPB_INT = 0x1 - CAPTURE B interrupt status bit was set.
9 CAPTUREA RW CAPTURE register A has grabbed the value in the counter

CAPA_INT = 0x1 - CAPTURE A interrupt status bit was set.
8 OVERFLOW RW COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.

OFLOW_INT = 0x1 - Overflow interrupt status bit was set.
7 COMPAREH RW COUNTER is greater than or equal to COMPARE register H.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
6 COMPAREG RW COUNTER is greater than or equal to COMPARE register G.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
5 COMPAREF RW COUNTER is greater than or equal to COMPARE register F.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
4 COMPAREE RW COUNTER is greater than or equal to COMPARE register E.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
3 COMPARED RW COUNTER is greater than or equal to COMPARE register D.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
2 COMPAREC RW COUNTER is greater than or equal to COMPARE register C.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
1 COMPAREB RW COUNTER is greater than or equal to COMPARE register B.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
0 COMPAREA RW COUNTER is greater than or equal to COMPARE register A.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.

STMINTSET - STIMER Interrupt registers: Set

Address:

  Instance 0 Address:   0x4000830C

Description:

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CAPTURED
0x0
CAPTUREC
0x0
CAPTUREB
0x0
CAPTUREA
0x0
OVERFLOW
0x0
COMPAREH
0x0
COMPAREG
0x0
COMPAREF
0x0
COMPAREE
0x0
COMPARED
0x0
COMPAREC
0x0
COMPAREB
0x0
COMPAREA
0x0

Bits Name RW Description
31:13 RSVD RO RESERVED.

12 CAPTURED RW CAPTURE register D has grabbed the value in the counter

CAPD_INT = 0x1 - Capture D interrupt status bit was set.
11 CAPTUREC RW CAPTURE register C has grabbed the value in the counter

CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set.
10 CAPTUREB RW CAPTURE register B has grabbed the value in the counter

CAPB_INT = 0x1 - CAPTURE B interrupt status bit was set.
9 CAPTUREA RW CAPTURE register A has grabbed the value in the counter

CAPA_INT = 0x1 - CAPTURE A interrupt status bit was set.
8 OVERFLOW RW COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.

OFLOW_INT = 0x1 - Overflow interrupt status bit was set.
7 COMPAREH RW COUNTER is greater than or equal to COMPARE register H.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
6 COMPAREG RW COUNTER is greater than or equal to COMPARE register G.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
5 COMPAREF RW COUNTER is greater than or equal to COMPARE register F.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
4 COMPAREE RW COUNTER is greater than or equal to COMPARE register E.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
3 COMPARED RW COUNTER is greater than or equal to COMPARE register D.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
2 COMPAREC RW COUNTER is greater than or equal to COMPARE register C.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
1 COMPAREB RW COUNTER is greater than or equal to COMPARE register B.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
0 COMPAREA RW COUNTER is greater than or equal to COMPARE register A.

COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.