Apollo Register Documentation  v2.4.2
BLEIF - BLE Interface

BLEIF Register Index

  0x00000000:   FIFO - FIFO Access Port
  0x00000100:   FIFOPTR - FIFO size and remaining slots open values
  0x00000104:   FIFOTHR - FIFO Threshold Configuration
  0x00000108:   FIFOPOP - FIFO POP register
  0x0000010C:   FIFOPUSH - FIFO PUSH register
  0x00000110:   FIFOCTRL - FIFO Control Register
  0x00000114:   FIFOLOC - FIFO Pointers
  0x00000200:   CLKCFG - I/O Clock Configuration
  0x0000020C:   CMD - Command and offset Register
  0x00000210:   CMDRPT - Command Repeat Register
  0x00000214:   OFFSETHI - High order offset bytes
  0x00000218:   CMDSTAT - Command status
  0x00000220:   INTEN - IO Master Interrupts: Enable
  0x00000224:   INTSTAT - IO Master Interrupts: Status
  0x00000228:   INTCLR - IO Master Interrupts: Clear
  0x0000022C:   INTSET - IO Master Interrupts: Set
  0x00000230:   DMATRIGEN - DMA Trigger Enable Register
  0x00000234:   DMATRIGSTAT - DMA Trigger Status Register
  0x00000238:   DMACFG - DMA Configuration Register
  0x0000023C:   DMATOTCOUNT - DMA Total Transfer Count
  0x00000240:   DMATARGADDR - DMA Target Address Register
  0x00000244:   DMASTAT - DMA Status Register
  0x00000248:   CQCFG - Command Queue Configuration Register
  0x0000024C:   CQADDR - CQ Target Read Address Register
  0x00000250:   CQSTAT - Command Queue Status Register
  0x00000254:   CQFLAGS - Command Queue Flag Register
  0x00000258:   CQSETCLEAR - Command Queue Flag Set/Clear Register
  0x0000025C:   CQPAUSEEN - Command Queue Pause Enable Register
  0x00000260:   CQCURIDX - IOM Command Queue current index value . Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue
  0x00000264:   CQENDIDX - IOM Command Queue current index value . Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue
  0x00000268:   STATUS - IOM Module Status Register
  0x00000300:   MSPICFG - SPI module master configuration
  0x00000304:   BLECFG - BLE Core Control
  0x00000308:   PWRCMD - BLE Power command interface
  0x0000030C:   BSTATUS - BLE Core status
  0x00000410:   BLEDBG - BLEIF Master Debug Register

FIFO - FIFO Access Port

Address:

  Instance 0 Address:   0x5000C000

Description:

Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C, and is used for data outuput from the IOM to external devices. These FIFO locations can be read and written directly. FIFO locations 0x20 - 0x3C provide read only access to the input fifo. These FIFO locations cannot be directly written by the MCU, and are updated only by the internal hardware. Writes to the FIFO0 will take effect immediately. The currently FIFO pointers in register FIFOLOC indicate the current offset into each FIFO0 for the read and write operations. Access to the FIFOs can only be done in word increments; Byte access and writes are not supported. For push and pop style access to FIFO0 can be done using the FIFOPOP and FIFOPUSH registers below.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFO
0x0

Bits Name RW Description
31:0 FIFO RW FIFO direct access. Only locations 0 - 3F will return valid information.


FIFOPTR - FIFO size and remaining slots open values

Address:

  Instance 0 Address:   0x5000C100

Description:

Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFO1REM
0x0
FIFO1SIZ
0x0
FIFO0REM
0x0
FIFO0SIZ
0x0

Bits Name RW Description
31:24 FIFO1REM RO The number of remaining data bytes slots currently in FIFO 1 (written by interface, read by MCU)

23:16 FIFO1SIZ RO The number of valid data bytes currently in FIFO 1 (written by interface, read by MCU)

15:8 FIFO0REM RO The number of remaining data bytes slots currently in FIFO 0 (written by MCU, read by interface)

7:0 FIFO0SIZ RO The number of valid data bytes currently in the FIFO 0 (written by MCU, read by interface)


FIFOTHR - FIFO Threshold Configuration

Address:

  Instance 0 Address:   0x5000C104

Description:

Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled, and also used during DMA to set the transfer size as a result of DMATHR trigger. The WTHR is used to indicate when there are more than WTHR bytes of open fifo locations available in the outgoing FIFO (FIFO0). The intended use to invoke an interrupt or DMA transfer that will refill the FIFO with a byte count up to this value. The RTHR is used to indicate when there are more than RTHR bytes in the incoming FIFO (FIFO1) and a data transfer of this size can be supported, either through direct POP of the FIFO, or through DMA. The value of both RTHR and WTHR are also used to set the data transfer size of DMA operations if DMATHR trigger is enabled.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
FIFOWTHR
0x0
RSVD
0x0
FIFORTHR
0x0

Bits Name RW Description
31:14 RSVD RO RESERVED

13:8 FIFOWTHR RW FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes, as indicated by the FIFO0REM field. This is intended to signal when a transfer of FIFOWTHR bytes can be done from the host to the IOM write fifo to support large IOM write operations.

7:6 RSVD RO RESERVED

5:0 FIFORTHR RW FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data, as indicated by the FIFO1SIZ field. This is intended to signal when a data transfer of FIFORTHR bytes can be done from the IOM module to the host via the read fifo to support large IOM read operations.


FIFOPOP - FIFO POP register

Address:

  Instance 0 Address:   0x5000C108

Description:

Will advance the internal read pointer of the incoming FIFO (FIFO1) when read, if POPWR is not active. If POPWR is active, a write to this register is needed to advance the internal FIFO pointer.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODOUT
0x0

Bits Name RW Description
31:0 FIFODOUT RW This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0), the fifo read pointer will be advanced by one word as a result of the read. If the POPWR bit is set (1), the fifo read pointer will only be advanced after a write operation to this register. The write data is ignored for this register. If less than a even word multiple is available, and the command is completed, the module will return the word containing these bytes and undetermined data in the unused fields of the word.


FIFOPUSH - FIFO PUSH register

Address:

  Instance 0 Address:   0x5000C10C

Description:

Will write new data into the outgoing FIFO and advance the internal write pointer.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODIN
0x0

Bits Name RW Description
31:0 FIFODIN RW This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes).


FIFOCTRL - FIFO Control Register

Address:

  Instance 0 Address:   0x5000C110

Description:

Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register, and also controls to reset the internal pointers of the FIFOs.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
FIFORSTN
0x1
POPWR
0x0

Bits Name RW Description
31:2 RSVD RO RESERVED

1 FIFORSTN RW Active low manual reset of the fifo. Write to 0 to reset fifo, and then write to 1 to remove the reset.

0 POPWR RW Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation, and will require a write to the FIFOPOP register to create a pop event. A value of '0' in this register will allow a pop event to occur on the read of the FIFOPOP register, and may cause inadvertant fifo pops when used in a debugging mode.


FIFOLOC - FIFO Pointers

Address:

  Instance 0 Address:   0x5000C114

Description:

Provides a read only value of the current read and write pointers. This register is read only and can be used alogn with the FIFO direct access method to determine the next data to be used for input and output functions.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
FIFORPTR
0x0
RSVD
0x0
FIFOWPTR
0x0

Bits Name RW Description
31:12 RSVD RO Reserved

11:8 FIFORPTR RW Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1), which is used to store read data returned from external devices during a read operation.

7:4 RSVD RO Reserved

3:0 FIFOWPTR RW Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0), which is used during write operations to external devices.


CLKCFG - I/O Clock Configuration

Address:

  Instance 0 Address:   0x5000C200

Description:

Provides clock related controls used internal to the BLEIF module, and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control. This register is also used to enable the clock, which must be done prior to performing any IO transactions.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DIV3
0x0
CLK32KEN
0x0
FSEL
0x0
RSVD
0x0
IOCLKEN
0x0

Bits Name RW Description
31:13 RSVD RO RESERVED

12 DIV3 RW Enable of the divide by 3 of the source IOCLK.

11 CLK32KEN RW Enable for the 32Khz clock to the BLE module

10:8 FSEL RW Select the input clock frequency.

MIN_PWR = 0x0 - Selects the minimum power clock. This setting should be used whenever the IOM is not active.
HFRC = 0x1 - Selects the HFRC as the input clock.
HFRC_DIV2 = 0x2 - Selects the HFRC / 2 as the input clock.
HFRC_DIV4 = 0x3 - Selects the HFRC / 4 as the input clock.
HFRC_DIV8 = 0x4 - Selects the HFRC / 8 as the input clock.
HFRC_DIV16 = 0x5 - Selects the HFRC / 16 as the input clock.
HFRC_DIV32 = 0x6 - Selects the HFRC / 32 as the input clock.
HFRC_DIV64 = 0x7 - Selects the HFRC / 64 as the input clock.
7:1 RSVD RO RESERVED

0 IOCLKEN RW Enable for the interface clock. Must be enabled prior to executing any IO operations.


CMD - Command and offset Register

Address:

  Instance 0 Address:   0x5000C20C

Description:

Writes to this register will start an IO transaction, as well as set various parameters for the command itself. Reads will return the command value written to the CMD register. To read the number of bytes that have yet to be transferred, refer to the CTSIZE field within the CMDSTAT register.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSETLO
0x0
RSRVD54
0x0
CMDSEL
0x0
TSIZE
0x0
CONT
0x0
OFFSETCNT
0x0
CMD
0x0

Bits Name RW Description
31:24 OFFSETLO RW This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command. Offset bytes are transferred starting from the highest byte first.

23:22 RSRVD54 RO Reserved

21:20 CMDSEL RW Command Specific selection information

19:8 TSIZE RW Defines the transaction size in bytes. The offset transfer is not included in this size.

7 CONT RW Contine to hold the bus after the current transaction if set to a 1 with a new command issued.

6:5 OFFSETCNT RW Number of offset bytes to use for the command - 0, 1, 2, 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register, and the low order byte is pulled from this register in the OFFSETLO field. Offset bytes are transmitted highest byte first. EG if offsetcnt == 3, OFFSETHI[15:8] will be transmitted first, then OFFSETHI[7:0] then OFFSETLO. If offsetcnt == 2, OFFSETHI[7:0] will be transmitted, then OFFSETLO. If offsetcnt == 1, only OFFSETLO will be transmitted. Offset bytes are always transmitted MSB first, regardless of the value of the LSB control bit within the module configuration.

4:0 CMD RW Command for submodule.

WRITE = 0x1 - Write command using count of offset bytes specified in the OFFSETCNT field
READ = 0x2 - Read command using count of offset bytes specified in the OFFSETCNT field

CMDRPT - Command Repeat Register

Address:

  Instance 0 Address:   0x5000C210

Description:

Will repeat the next command for CMDRPT number of times. If CMDRPT is set to 1, the next command will be done 2 times in series. A repeat count of up to 31 is possible. Each command will be done as a seperate command, but the data will be treated as packed, and aligned to byte boundaries. This differs when executing seperate commands without the CMDRPT set, as the data for each transaction is word aligned and any unused byte locations will be filled with 0 for read operations, or discarded for write operations. For repeated commands (CMDRPT is nonzero), the data is packed and no bytes will be filled or discarded until the final command is done. The register value is decremented for each repeated command and at the end of the repeated command set, will be set to zero. If subsequent commands are to be repeated, this register must be written again.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CMDRPT
0x0

Bits Name RW Description
31:5 RSVD RO RESERVED

4:0 CMDRPT RW Count of number of times to repeat the next command.


OFFSETHI - High order offset bytes

Address:

  Instance 0 Address:   0x5000C214

Description:

Provides the high order bytes of 2 or 3 byte offset transactions of the current command. Usage of these bytes is dependant on the offsetcnt field in the CMD register. If the offsetcnt == 3, the data located at OFFSETHI[15:0] will first be transmitted, followed by OFFSETHI[7:0], followed by OFFSETLO (in the CMD register) prior to sending or receiving any transaction data (if programed via TSIZE field in the CMD register). The offset bytes are always transmitted MSB first for all modules.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
OFFSETHI
0x0

Bits Name RW Description
31:16 RSVD RO Reserved

15:0 OFFSETHI RW Holds the high order bytes of the 2 or 3 byte offset phase of a transaction.


CMDSTAT - Command status

Address:

  Instance 0 Address:   0x5000C218

Description:

Provides staus on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM. These are read only fields and writes to the registers are ignored.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD0
0x0
CTSIZE
0x0
CMDSTAT
0x0
CCMD
0x0

Bits Name RW Description
31:20 RSRVD0 RO Reserved

19:8 CTSIZE RO The current number of bytes still to be transferred with this command. This field will count down to zero.

7:5 CMDSTAT RO The current status of the command execution.

ERR = 0x1 - Error encountered with command
ACTIVE = 0x2 - Actively processing command
IDLE = 0x4 - Idle state, no active command, no error
WAIT = 0x6 - Command in progress, but waiting on data from host
4:0 CCMD RO current command that is being executed


INTEN - IO Master Interrupts: Enable

Address:

  Instance 0 Address:   0x5000C220

Description:

Set bits in this register to allow this module to generate the corresponding interrupt.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
B2MSHUTDN
0x0
B2MACTIVE
0x0
B2MSLEEP
0x0
CQERR
0x0
CQUPD
0x0
CQPAUSED
0x0
DERR
0x0
DCMP
0x0
BLECSSTAT
0x0
BLECIRQ
0x0
ICMD
0x0
IACC
0x0
B2MST
0x0
FOVFL
0x0
FUNDFL
0x0
THR
0x0
CMDCMP
0x0

Bits Name RW Description
31:17 RSVD RO RESERVED

16 B2MSHUTDN RW Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)

15 B2MACTIVE RW Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)

14 B2MSLEEP RW The B2M_STATE from the BLE Core transitioned into the sleep state

13 CQERR RW Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions

12 CQUPD RW Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.

11 CQPAUSED RW Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.

10 DERR RW DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.

9 DCMP RW DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state

8 BLECSSTAT RW BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high.

7 BLECIRQ RW BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core.

6 ICMD RW illegal command interrupt. Asserted when a command is written when an active command is in progress.

5 IACC RW illegal FIFO access interrupt. Asserted when there is a overflow or underflow event

4 B2MST RW B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core.

3 FOVFL RW Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop.

2 FUNDFL RW Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO.

1 THR RW FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.

0 CMDCMP RW Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.


INTSTAT - IO Master Interrupts: Status

Address:

  Instance 0 Address:   0x5000C224

Description:

Read bits from this register to discover the cause of a recent interrupt.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
B2MSHUTDN
0x0
B2MACTIVE
0x0
B2MSLEEP
0x0
CQERR
0x0
CQUPD
0x0
CQPAUSED
0x0
DERR
0x0
DCMP
0x0
BLECSSTAT
0x0
BLECIRQ
0x0
ICMD
0x0
IACC
0x0
B2MST
0x0
FOVFL
0x0
FUNDFL
0x0
THR
0x0
CMDCMP
0x0

Bits Name RW Description
31:17 RSVD RO RESERVED

16 B2MSHUTDN RW Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)

15 B2MACTIVE RW Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)

14 B2MSLEEP RW The B2M_STATE from the BLE Core transitioned into the sleep state

13 CQERR RW Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions

12 CQUPD RW Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.

11 CQPAUSED RW Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.

10 DERR RW DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.

9 DCMP RW DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state

8 BLECSSTAT RW BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high.

7 BLECIRQ RW BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core.

6 ICMD RW illegal command interrupt. Asserted when a command is written when an active command is in progress.

5 IACC RW illegal FIFO access interrupt. Asserted when there is a overflow or underflow event

4 B2MST RW B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core.

3 FOVFL RW Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop.

2 FUNDFL RW Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO.

1 THR RW FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.

0 CMDCMP RW Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.


INTCLR - IO Master Interrupts: Clear

Address:

  Instance 0 Address:   0x5000C228

Description:

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
B2MSHUTDN
0x0
B2MACTIVE
0x0
B2MSLEEP
0x0
CQERR
0x0
CQUPD
0x0
CQPAUSED
0x0
DERR
0x0
DCMP
0x0
BLECSSTAT
0x0
BLECIRQ
0x0
ICMD
0x0
IACC
0x0
B2MST
0x0
FOVFL
0x0
FUNDFL
0x0
THR
0x0
CMDCMP
0x0

Bits Name RW Description
31:17 RSVD RO RESERVED

16 B2MSHUTDN RW Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)

15 B2MACTIVE RW Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)

14 B2MSLEEP RW The B2M_STATE from the BLE Core transitioned into the sleep state

13 CQERR RW Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions

12 CQUPD RW Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.

11 CQPAUSED RW Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.

10 DERR RW DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.

9 DCMP RW DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state

8 BLECSSTAT RW BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high.

7 BLECIRQ RW BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core.

6 ICMD RW illegal command interrupt. Asserted when a command is written when an active command is in progress.

5 IACC RW illegal FIFO access interrupt. Asserted when there is a overflow or underflow event

4 B2MST RW B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core.

3 FOVFL RW Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop.

2 FUNDFL RW Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO.

1 THR RW FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.

0 CMDCMP RW Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.


INTSET - IO Master Interrupts: Set

Address:

  Instance 0 Address:   0x5000C22C

Description:

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
B2MSHUTDN
0x0
B2MACTIVE
0x0
B2MSLEEP
0x0
CQERR
0x0
CQUPD
0x0
CQPAUSED
0x0
DERR
0x0
DCMP
0x0
BLECSSTAT
0x0
BLECIRQ
0x0
ICMD
0x0
IACC
0x0
B2MST
0x0
FOVFL
0x0
FUNDFL
0x0
THR
0x0
CMDCMP
0x0

Bits Name RW Description
31:17 RSVD RO RESERVED

16 B2MSHUTDN RW Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)

15 B2MACTIVE RW Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)

14 B2MSLEEP RW The B2M_STATE from the BLE Core transitioned into the sleep state

13 CQERR RW Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions

12 CQUPD RW Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.

11 CQPAUSED RW Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.

10 DERR RW DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.

9 DCMP RW DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state

8 BLECSSTAT RW BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high.

7 BLECIRQ RW BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core.

6 ICMD RW illegal command interrupt. Asserted when a command is written when an active command is in progress.

5 IACC RW illegal FIFO access interrupt. Asserted when there is a overflow or underflow event

4 B2MST RW B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core.

3 FOVFL RW Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop.

2 FUNDFL RW Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO.

1 THR RW FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.

0 CMDCMP RW Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.


DMATRIGEN - DMA Trigger Enable Register

Address:

  Instance 0 Address:   0x5000C230

Description:

Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be transferred via the DMA operation, and can be used to adjust the latency of data to/from the IOM module to/from the dma target. DMA transfers are broken into smaller transfers internally of up to 16 bytes each, and multiple trigger events can be used to complete the entire programmed DMA transfer.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DTHREN
0x0
DCMDCMPEN
0x0

Bits Name RW Description
31:2 RSVD RO RESERVED.

1 DTHREN RW Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes), the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO, and will transfer (WTHR/4) number of words or, if the number of words left to transfer is less than the WTHR value, will transfer the remaining byte count. For P2M DMA operations, the trigger will assert when the read FIFO has (RTHR/4) words available in the read FIFO, and will transfer (RTHR/4) words to SRAM. This trigger will NOT assert when the transaction completes and there are less than RTHR bytes left in the fifo, since the RTHR has not been reached. In this case, enabling the CMDCMP trigger will transfer the remaining data from the commmand. If the CMDCMP trigger is not enabled, the module will initiate a transfer when the amount of data in the FIFO is equal to or greater than the remaining data in the DMA. In cases where one DMA setup covers multiple commands, this will only occur at the end of the last transaction when the DMA is near complete.

0 DCMDCMPEN RW Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered, the number of words transferred will be the lesser of the remaining TOTCOUNT bytes, or the number of bytes in the FIFO when the command completed. If this is disabled, and the number of bytes in the FIFO is equal or greater than the TOTCOUNT bytes, a transfer of TOTCOUNT bytes will be done to ensure read data is stored when the DMA is completed.


DMATRIGSTAT - DMA Trigger Status Register

Address:

  Instance 0 Address:   0x5000C234

Description:

Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DTOTCMP
0x0
DTHR
0x0
DCMDCMP
0x0

Bits Name RW Description
31:3 RSVD RO RESERVED.

2 DTOTCMP RO DMA triggered when DCMDCMP = 0, and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is disabled and there is enough data in the FIFO to complete the DMA operation.

1 DTHR RO Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA.

0 DCMDCMP RO Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA.


DMACFG - DMA Configuration Register

Address:

  Instance 0 Address:   0x5000C238

Description:

Configuration control of the DMA process, including the direction of DMA, and enablement of DMA

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DPWROFF
0x0
DMAPRI
0x0
RSVD
0x0
DMADIR
0x0
DMAEN
0x0

Bits Name RW Description
31:10 RSVD RO RESERVED.

9 DPWROFF RW Power off module after DMA is complete. If this bit is active, the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain, power down will not be performed.

DIS = 0x0 - Power off disabled
EN = 0x1 - Power off enabled
8 DMAPRI RW Sets the Priority of the DMA request

LOW = 0x0 - Low Priority (service as best effort)
HIGH = 0x1 - High Priority (service immediately)
7:2 RSVD RO RESERVED.

1 DMADIR RW Direction

P2M = 0x0 - Peripheral to Memory (SRAM) transaction. To be set when doing IOM read operations, ie reading data from external devices.
M2P = 0x1 - Memory to Peripheral transaction. To be set when doing IOM write operations, ie writing data to external devices.
0 DMAEN RW DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command

DIS = 0x0 - Disable DMA Function
EN = 0x1 - Enable DMA Function

DMATOTCOUNT - DMA Total Transfer Count

Address:

  Instance 0 Address:   0x5000C23C

Description:

Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred, and will be 0 at the completion of the DMA operation.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVDD
0x0
TOTCOUNT
0x0

Bits Name RW Description
31:12 RSRVDD RO Reserved

11:0 TOTCOUNT RW Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA.


DMATARGADDR - DMA Target Address Register

Address:

  Instance 0 Address:   0x5000C240

Description:

The source or destination address internal the SRAM for the DMA data. For write operations, this can only be SRAM data (ADDR bit 28 = 1); For read operations, this can ve either SRAM or FLASH (ADDR bit 28 = 0)

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
TARGADDR28
0x0
RSVD
0x0
TARGADDR
0x0

Bits Name RW Description
31:29 RSVD RO Reserved

28 TARGADDR28 RW Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written. Setting to '1' will select the SRAM. Setting to '0' will select the flash

27:20 RSVD RO Reserved

19:0 TARGADDR RW Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment, and does not have to be word aligned. In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written.


DMASTAT - DMA Status Register

Address:

  Instance 0 Address:   0x5000C244

Description:

Status of the DMA operation currently in progress.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DMAERR
0x0
DMACPL
0x0
DMATIP
0x0

Bits Name RW Description
31:3 RSVD RO RESERVED.

2 DMAERR RW DMA Error. This active high bit signals that an error was encountered during the DMA operation.

1 DMACPL RW DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0.

0 DMATIP RO DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done. This bit is read only.


CQCFG - Command Queue Configuration Register

Address:

  Instance 0 Address:   0x5000C248

Description:

Controls parameters and options for execution of the command queue operation. To enable command queue, create this in memory, set the address, and enable it with a write to CQEN

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CQPRI
0x0
CQEN
0x0

Bits Name RW Description
31:2 RSVD RO RESERVED.

1 CQPRI RW Sets the Priority of the command queue dma request.

LOW = 0x0 - Low Priority (service as best effort)
HIGH = 0x1 - High Priority (service immediately)
0 CQEN RW Command queue enable. When set, will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well.

DIS = 0x0 - Disable CQ Function
EN = 0x1 - Enable CQ Function

CQADDR - CQ Target Read Address Register

Address:

  Instance 0 Address:   0x5000C24C

Description:

The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses, and is the live version of the register. The register can also be written by the Command Queue operation itself, allowing the relocation of successive CQ fetches. In this case, the new CQ address will be used for the next CQ address/data fetch

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSRVD2
0x0
CQADDR28
0x0
RSRVD1
0x0
CQADDR
0x0
RSRVD0
0x0

Bits Name RW Description
31:29 RSRVD2 RO Reserved

28 CQADDR28 RW Bit 28 of target byte address for source of CQ (read only). Used to denote Flash (0) or SRAM (1) access

27:20 RSRVD1 RO Reserved

19:2 CQADDR RW Bits 19:2 of target byte address for source of CQ (read only). The buffer must be aligned on a word boundary

1:0 RSRVD0 RO Reserved


CQSTAT - Command Queue Status Register

Address:

  Instance 0 Address:   0x5000C250

Description:

Provides the status of the command queue operation. If the command queue is disabled, these bits will be cleared. The bits are read only

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CQERR
0x0
CQPAUSED
0x0
CQTIP
0x0

Bits Name RW Description
31:3 RSVD RO RESERVED.

2 CQERR RW Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation.

1 CQPAUSED RO Command queue operation is currently paused.

0 CQTIP RO Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event.


CQFLAGS - Command Queue Flag Register

Address:

  Instance 0 Address:   0x5000C254

Description:

Provides the current status of the SWFLAGS (bits 7:0) and the hardware generated flags (15:8). A '1' will pause the CQ operation if it the same bit is enabled in the CQPAUSEEN register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CQIRQMASK
0x0
CQFLAGS
0x0

Bits Name RW Description
31:16 CQIRQMASK RW Provides for a per-bit mask of the flags used to invoke an interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt, if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE

15:0 CQFLAGS RO Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status.


CQSETCLEAR - Command Queue Flag Set/Clear Register

Address:

  Instance 0 Address:   0x5000C258

Description:

Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields, allowing for setting, clearing or toggling the value in the software flags. Priority when the same bit is enabled in each field is toggle, then set, then clear.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CQFCLR
0x0
CQFTGL
0x0
CQFSET
0x0

Bits Name RW Description
31:24 RSVD RO Reserved

23:16 CQFCLR WO Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field

15:8 CQFTGL WO Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field

7:0 CQFSET WO Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field


CQPAUSEEN - Command Queue Pause Enable Register

Address:

  Instance 0 Address:   0x5000C25C

Description:

Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1', CQ processing will halt until either value is changed to '0'.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CQPEN
0x0

Bits Name RW Description
31:16 RSVD RO Reserved

15:0 CQPEN RW Enables the specified event to pause command processing when active

CNTEQ = 0x8000 - Pauses command queue processing when HWCNT matches SWCNT
BLEXOREN = 0x4000 - Pause command queue when input BLE bit XORed with SWFLAG4 is '1'
IOMXOREN = 0x2000 - Pause command queue when input IOM bit XORed with SWFLAG3 is '1'
GPIOXOREN = 0x1000 - Pause command queue when input GPIO irq_bit XORed with SWFLAG2 is '1'
MSPI1XNOREN = 0x800 - Pause command queue when input MSPI1 bit XNORed with SWFLAG1 is '1'
MSPI0XNOREN = 0x400 - Pause command queue when input MSPI0 bit XNORed with SWFLAG0 is '1'
MSPI1XOREN = 0x200 - Pause command queue when input MSPI1 bit XORed with SWFLAG1 is '1'
MSPI0XOREN = 0x100 - Pause command queue when input MSPI0 bit XORed with SWFLAG0 is '1'
SWFLAGEN7 = 0x80 - Pause the command queue when software flag bit 7 is '1'.
SWFLAGEN6 = 0x40 - Pause the command queue when software flag bit 7 is '1'
SWFLAGEN5 = 0x20 - Pause the command queue when software flag bit 7 is '1'
SWFLAGEN4 = 0x10 - Pause the command queue when software flag bit 7 is '1'
SWFLAGEN3 = 0x8 - Pause the command queue when software flag bit 7 is '1'
SWFLAGEN2 = 0x4 - Pause the command queue when software flag bit 7 is '1'
SWFLAGEN1 = 0x2 - Pause the command queue when software flag bit 7 is '1'
SWFLGEN0 = 0x1 - Pause the command queue when software flag bit 7 is '1'

CQCURIDX - IOM Command Queue current index value . Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue

Address:

  Instance 0 Address:   0x5000C260

Description:

Current index value, targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and this current index equals the CQENDIDX register value. This will only pause when the values are equal.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CQCURIDX
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED

7:0 CQCURIDX RW Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN.


CQENDIDX - IOM Command Queue current index value . Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue

Address:

  Instance 0 Address:   0x5000C264

Description:

End index value, targeted to be written by software to indicate the last valid register pair contained within the command queue. rgister write operations within the command queue. This is compared to the CQCURIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and this current index equals the CQCURIDX register value. This will only pause when the values are equal.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CQENDIDX
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED

7:0 CQENDIDX RW Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN.


STATUS - IOM Module Status Register

Address:

  Instance 0 Address:   0x5000C268

Description:

General status of the IOM module command execution.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
IDLEST
0x0
CMDACT
0x0
ERR
0x0

Bits Name RW Description
31:3 RSVD RO RESERVED

2 IDLEST RO indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability, or as the command gets propagated into the logic from the registers.

IDLE = 0x1 - The I/O state machine is in the idle state.
1 CMDACT RO Indicates if the active I/O Command is currently processing a transaction, or command is complete, but the FIFO pointers are still syncronizing internally. This bit will go high at the start of the transaction, and will go low when the command is complete, and the data and pointers within the FIFO have been syncronized.

ACTIVE = 0x1 - An I/O command is active. Indicates the active module has an active command and is processing this. De-asserted when the command is completed.
0 ERR RO Bit has been deprecated. Please refer to the other error indicators. This will always return 0.

ERROR = 0x1 - Bit has been deprecated and will always return 0.

MSPICFG - SPI module master configuration

Address:

  Instance 0 Address:   0x5000C300

Description:

Controls the configuration of the SPI master module, including POL/PHA, LSB, flow control, and delays for MISO and MOSI

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
MSPIRST
0x1
DOUTDLY
0x0
DINDLY
0x0
SPILSB
0x0
RDFCPOL
0x0
WTFCPOL
0x0
RSVD
0x0
RDFC
0x0
WTFC
0x0
RSVD
0x0
FULLDUP
0x0
SPHA
0x0
SPOL
0x0

Bits Name RW Description
31 RSVD RO RESERVED

30 MSPIRST RW Bit is deprecated. setting it will have no effect.

29:27 DOUTDLY RW Delay tap to use for the output signal (MOSI). This give more hold time on the output data.

26:24 DINDLY RW Delay tap to use for the input signal (MISO). This gives more hold time on the input data.

23 SPILSB RW Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first.

MSB = 0x0 - Send and receive MSB bit first
LSB = 0x1 - Send and receive LSB bit first
22 RDFCPOL RW Selects the read flow control signal polarity. When set, the clock will be held low until the flow control is de-asserted.

NORMAL = 0x0 - SPI_STATUS signal from BLE Core high(1) creates flow control and new read spi transactions will not be started until the signal goes low.(default)
INVERTED = 0x1 - SPI_STATUS signal from BLE Core low(0) creates flow control and new read spi transactions will not be started until the signal goes high.
21 WTFCPOL RW Selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of this bit. (For example: WTFCPOL = 0 will allow a SPI_STATUS=1 to pause transfers).

NORMAL = 0x0 - SPI_STATUS signal from BLE Core high(1) creates flow control and new write spi transactions will not be started until the signal goes low.(default)
INVERTED = 0x1 - SPI_STATUS signal from BLE Core high(1) creates low(0) control and new write spi transactions will not be started until the signal goes high.
20:18 RSVD R0 Reserved

17 RDFC RW Enables flow control of new read transactions based on the SPI_STATUS signal from the BLE Core.

DIS = 0x0 - Read mode flow control disabled.
EN = 0x1 - Read mode flow control enabled.
16 WTFC RW Enables flow control of new write transactions based on the SPI_STATUS signal from the BLE Core.

DIS = 0x0 - Write mode flow control disabled.
EN = 0x1 - Write mode flow control enabled.
15:3 RSVD R0 Reserved

2 FULLDUP RW Full Duplex mode. Capture read data during writes operations

1 SPHA RW Selects the SPI phase; When 1, will shift the sampling edge by 1/2 clock.

SAMPLE_LEADING_EDGE = 0x0 - Sample on the leading (first) clock edge, rising or falling dependant on the value of SPOL
SAMPLE_TRAILING_EDGE = 0x1 - Sample on the trailing (second) clock edge, rising of falling dependant on the value of SPOL
0 SPOL RW This bit selects SPI polarity.

CLK_BASE_0 = 0x0 - The initial value of the clock is 0.
CLK_BASE_1 = 0x1 - The initial value of the clock is 1.

BLECFG - BLE Core Control

Address:

  Instance 0 Address:   0x5000C304

Description:

Provides control of isolation and IO signals between the interface module and the BLE Core.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
SPIISOCTL
0x0
PWRISOCTL
0x0
STAYASLEEP
0x0
FRCCLK
0x0
MCUFRCSLP
0x0
WT4ACTOFF
0x0
BLEHREQCTL
0x0
DCDCFLGCTL
0x0
WAKEUPCTL
0x0
BLERSTN
0x0
PWRSMEN
0x0

Bits Name RW Description
31:16 RSVD RO RESERVED

15:14 SPIISOCTL RW Configuration of BLEH isolation controls for SPI related signals.

ON = 0x3 - SPI signals from BLE Core to/from MCU Core are isolated.
OFF = 0x2 - SPI signals from BLE Core to/from MCU Core are not isolated.
AUTO = 0x0 - SPI signals from BLE Core to/from MCU Core are automatically isolated by the logic
13:12 PWRISOCTL RW Configuration of BLEH isolation control for power related signals.

ON = 0x3 - BLEH power signal isolation to on (isolated).
OFF = 0x2 - BLEH power signal isolation to off (not isolated).
AUTO = 0x0 - BLEH Power signal isolation is controlled automatically through the interface logic
11 STAYASLEEP RW Set to prevent the BLE power control module from waking up the BLE Core after going into power down. To be used for graceful shutdown, set by software prior to powering off and will allow assertion of reset from sleep state.

10 FRCCLK RW Force the clock in the BLEIF to be always running

9 MCUFRCSLP RW Force power state machine to go to the sleep state. Intended for debug only. Has no effect on the actual BLE Core state, only the state of the BLEIF interface state machine.

8 WT4ACTOFF RW Debug control of BLEIF power state machine. Allows transition into the active state in the BLEIF state without waiting for dcdc req from BLE Core.

7:6 BLEHREQCTL RW BLEH power on request override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic.

ON = 0x3 - BLEH Power-on reg signal is set to on (1).
OFF = 0x2 - BLEH Power-on signal is set to off (0).
AUTO = 0x0 - BLEH Power-on signal is controlled by the PWRSM logic and automatically controlled
5:4 DCDCFLGCTL RW DCDCFLG signal override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic.

ON = 0x3 - DCDC Flag signal is set to on (1).
OFF = 0x2 - DCDC Flag signal is set to off (0).
AUTO = 0x0 - DCDC Flag signal is controlled by the PWRSM logic and automatically controlled
3:2 WAKEUPCTL RW WAKE signal override. Controls the source of the WAKE signal to the BLE Core.

ON = 0x3 - Wake signal is set to on (1).
OFF = 0x2 - Wake signal is set to off (0).
AUTO = 0x0 - Wake signal is controlled by the PWRSM logic and automatically controlled
1 BLERSTN RW Reset line to the BLE Core. This will reset the BLE core when asserted ('0') and must be written to '1' prior to performing any BTLE related operations to the core.

ACTIVE = 0x1 - The reset signal is active (0)
INACTIVE = 0x0 - The reset signal is inactive (1)
0 PWRSMEN RW Enable the power state machine for automatic sequencing and control of power states of the BLE Core module.

ON = 0x1 - Internal power state machine is enabled and will sequence the BLEH power domain as indicated in the design document. Overrides for the power signals are not enabled.
OFF = 0x0 - Internal power state machine is disabled and will not sequence the BLEH power domain. The values of the overrides will be used to drive the output sequencing signals

PWRCMD - BLE Power command interface

Address:

  Instance 0 Address:   0x5000C308

Description:

Sends power related commands to the power state machine in the BLE IF module.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
RESTART
0x0
WAKEREQ
0x0

Bits Name RW Description
31:2 RSVD RO Reserved

1 RESTART WO Restart the BLE Core after going into the shutdown state. Only valid when in the shutdown state.

0 WAKEREQ WO Wake request from the MCU. When asserted (1), the BLE Interface logic will assert the wakeup request signal to the BLE Core. Only recognized when in the sleep state


BSTATUS - BLE Core status

Address:

  Instance 0 Address:   0x5000C30C

Description:

Status of the BLE Core interface signals

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
BLEHREQ
0x0
BLEHACK
0x0
PWRST
0x0
BLEIRQ
0x0
WAKEUP
0x0
DCDCFLAG
0x0
DCDCREQ
0x0
SPISTATUS
0x0
B2MSTATE
0x0

Bits Name RW Description
31:13 RSVD RO RESERVED

12 BLEHREQ RO Value of the BLEHREQ signal to the power control unit. The BLEHREQ signal is sent from the BLEIF module to the power control module to request the BLEH power up. When the BLEHACK signal is asserted, BLEH power is stable and ready for use.

11 BLEHACK RO Value of the BLEHACK signal from the power control unit. If the signal is '1', the BLEH power is active and ready for use.

10:8 PWRST RO Current status of the power state machine

OFF = 0x0 - Internal power state machine is disabled and will not sequence the BLEH power domain. The values of the overrides will be used to drive the output sequencing signals
INIT = 0x1 - Initialization state. BLEH not powered
PWRON = 0x2 - Waiting for the powerup of the BLEH
ACTIVE = 0x3 - The BLE Core is powered and active
SLEEP = 0x6 - The BLE Core has entered sleep mode and the power request is inactive
SHUTDOWN = 0x4 - The BLE Core is in shutdown mode
7 BLEIRQ RO Status of the BLEIRQ signal from the BLE Core. A value of 1 idicates that read data is available in the core and a read operation needs to be performed.

6 WAKEUP RO Value of the WAKEUP signal to the BLE Core . The WAKEUP signals is sent from the BLEIF to the BLECORE to request the BLE Core transition from sleep state to active state.

5 DCDCFLAG RO Value of the DCDCFLAG signal to the BLE Core. The DCDCFLAG is a signal to the BLE Core indicating that the BLEH ppower is active.

4 DCDCREQ RO Value of the DCDCREQ signal from the BLE Core. The DCDCREQ signal is sent from the core to the BLEIF module when the BLE core requires BLEH power to be active. When activated, this is indicated by DCDCFLAG going to 1.

3 SPISTATUS RO Value of the SPISTATUS signal from the BLE Core. The signal is asserted when the BLE Core is able to accept write data via the SPI interface. Data should be transmitted to the BLE core only when this signal is 1. The hardware will automatically wait for this signal prior to performing a write operation if flow control is active.

2:0 B2MSTATE RO State of the BLE Core logic.

RESET = 0x0 - Reset State
Shutdown = 0x0 - Shutdown state
Sleep = 0x1 - Sleep state.
Standby = 0x2 - Standby State
Idle = 0x3 - Idle state
Active = 0x4 - Active state.

BLEDBG - BLEIF Master Debug Register

Address:

  Instance 0 Address:   0x5000C410

Description:

Debug control

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBGDATA
0x0
APBCLKON
0x0
IOCLKON
0x0
DBGEN
0x0

Bits Name RW Description
31:3 DBGDATA RW Debug data

2 APBCLKON RW APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed.

1 IOCLKON RW IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed.

0 DBGEN RW Debug Enable. Setting this bit will enable the update of data within this register, otherwise it is clock gated for power savings