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Apollo Register Documentation v2.4.2
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Instance 0 Address: | 0x40010000 |
This register controls the pad configuration controls for PAD3 through PAD0. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD3PWRUP
0x0 |
PAD3FNCSEL
0x3 |
PAD3STRNG
0x0 |
PAD3INPEN
0x0 |
PAD3PULL
0x0 |
RSVD
0x0 |
PAD2FNCSEL
0x3 |
PAD2STRNG
0x0 |
PAD2INPEN
0x0 |
PAD2PULL
0x0 |
PAD1RSEL
0x0 |
PAD1FNCSEL
0x3 |
PAD1STRNG
0x0 |
PAD1INPEN
0x0 |
PAD1PULL
0x0 |
PAD0RSEL
0x0 |
PAD0FNCSEL
0x3 |
PAD0STRNG
0x0 |
PAD0INPEN
0x0 |
PAD0PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | RSVD | RO | RESERVED |
30 | PAD3PWRUP | RW | Pad 3 VDD power switch enable DIS = 0x0 - Power switch disabled EN = 0x1 - Power switch enabled (switched to VDD) |
29:27 | PAD3FNCSEL | RW | Pad 3 function select UA0RTS = 0x0 - Configure as the UART0 RTS output SLnCE = 0x1 - Configure as the IOSLAVE SPI nCE signal NCE3 = 0x2 - IOM/MSPI nCE group 3 GPIO3 = 0x3 - Configure as GPIO3 RSVD = 0x4 - Reserved MSPI7 = 0x5 - MSPI data connection 7 TRIG1 = 0x6 - Configure as the ADC Trigger 1 signal I2S_WCLK = 0x7 - Configure as the PDM I2S Word Clock input |
26 | PAD3STRNG | RW | Pad 3 drive strength. LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD3INPEN | RW | Pad 3 input enable. DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD3PULL | RW | Pad 3 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:22 | RSVD | RO | RESERVED |
21:19 | PAD2FNCSEL | RW | Pad 2 function select RSVD0 = 0x0 - Reserved SLMISO = 0x1 - Configure as the IOSLAVE SPI MISO signal UART0RX = 0x2 - Configure as the UART0 RX input GPIO2 = 0x3 - Configure as GPIO2 RSVD4 = 0x4 - Reserved MSPI6 = 0x5 - CMSPI data connection 6 RSVD6 = 0x6 - Reserved NCE2 = 0x7 - IOM/MSPI nCE group 2 |
18 | PAD2STRNG | RW | Pad 2 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD2INPEN | RW | Pad 2 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD2PULL | RW | Pad 2 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:14 | PAD1RSEL | RW | Pad 1 pullup resistor selection. PULL1_5K = 0x0 - Pullup is ~1.5 KOhms PULL6K = 0x1 - Pullup is ~6 KOhms PULL12K = 0x2 - Pullup is ~12 KOhms PULL24K = 0x3 - Pullup is ~24 KOhms |
13:11 | PAD1FNCSEL | RW | Pad 1 function select SLSDAWIR3 = 0x0 - Configure as the IOSLAVE I2C SDA or SPI WIR3 signal SLMOSI = 0x1 - Configure as the IOSLAVE SPI MOSI signal UART0TX = 0x2 - Configure as the UART0 TX output signal GPIO1 = 0x3 - Configure as GPIO1 RSVD4 = 0x4 - Reserved MSPI5 = 0x5 - MSPI data connection 5 RSVD6 = 0x6 - Reserved NCE1 = 0x7 - IOM/MSPI nCE group 1 |
10 | PAD1STRNG | RW | Pad 1 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD1INPEN | RW | Pad 1 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD1PULL | RW | Pad 1 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:6 | PAD0RSEL | RW | Pad 0 pullup resistor selection. PULL1_5K = 0x0 - Pullup is ~1.5 KOhms PULL6K = 0x1 - Pullup is ~6 KOhms PULL12K = 0x2 - Pullup is ~12 KOhms PULL24K = 0x3 - Pullup is ~24 KOhms |
5:3 | PAD0FNCSEL | RW | Pad 0 function select SLSCL = 0x0 - Configure as the IOSLAVE I2C SCL signal SLSCK = 0x1 - Configure as the IOSLAVE SPI SCK signal CLKOUT = 0x2 - Configure as the CLKOUT signal GPIO0 = 0x3 - Configure as GPIO0 RSVD4 = 0x4 - Reserved MSPI4 = 0x5 - MSPI data connection 4 RSVD6 = 0x6 - Reserved NCE0 = 0x7 - IOM/MSPI nCE group 0 |
2 | PAD0STRNG | RW | Pad 0 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD0INPEN | RW | Pad 0 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD0PULL | RW | Pad 0 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x40010004 |
This register controls the pad configuration controls for PAD7 through PAD4. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD7FNCSEL
0x3 |
PAD7STRNG
0x0 |
PAD7INPEN
0x0 |
PAD7PULL
0x0 |
PAD6RSEL
0x0 |
PAD6FNCSEL
0x3 |
PAD6STRNG
0x0 |
PAD6INPEN
0x0 |
PAD6PULL
0x0 |
PAD5RSEL
0x0 |
PAD5FNCSEL
0x3 |
PAD5STRNG
0x0 |
PAD5INPEN
0x0 |
PAD5PULL
0x0 |
RSVD
0x0 |
PAD4FNCSEL
0x3 |
PAD4STRNG
0x0 |
PAD4INPEN
0x0 |
PAD4PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:30 | RSVD | RO | RESERVED |
29:27 | PAD7FNCSEL | RW | Pad 7 function select NCE7 = 0x0 - IOM/MSPI nCE group 7 M0MOSI = 0x1 - Configure as the IOMSTR0 SPI MOSI signal CLKOUT = 0x2 - Configure as the CLKOUT signal GPIO7 = 0x3 - Configure as GPIO7 TRIG0 = 0x4 - Configure as the ADC Trigger 0 signal UART0TX = 0x5 - Configure as the UART0 TX output signal RSVD = 0x6 - Reserved CT19 = 0x7 - CTIMER connection 19 |
26 | PAD7STRNG | RW | Pad 7 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD7INPEN | RW | Pad 7 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD7PULL | RW | Pad 7 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:22 | PAD6RSEL | RW | Pad 6 pullup resistor selection. PULL1_5K = 0x0 - Pullup is ~1.5 KOhms PULL6K = 0x1 - Pullup is ~6 KOhms PULL12K = 0x2 - Pullup is ~12 KOhms PULL24K = 0x3 - Pullup is ~24 KOhms |
21:19 | PAD6FNCSEL | RW | Pad 6 function select M0SDAWIR3 = 0x0 - Configure as the IOMSTR0 I2C SDA or SPI WIR3 signal M0MISO = 0x1 - Configure as the IOMSTR0 SPI MISO signal UA0CTS = 0x2 - Configure as the UART0 CTS input signal GPIO6 = 0x3 - Configure as GPIO6 RSVD4 = 0x4 - Reserved CT10 = 0x5 - CTIMER connection 10 RSVD6 = 0x6 - Reserved I2S_DAT = 0x7 - Configure as the PDM I2S Data output signal |
18 | PAD6STRNG | RW | Pad 6 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD6INPEN | RW | Pad 6 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD6PULL | RW | Pad 6 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:14 | PAD5RSEL | RW | Pad 5 pullup resistor selection. PULL1_5K = 0x0 - Pullup is ~1.5 KOhms PULL6K = 0x1 - Pullup is ~6 KOhms PULL12K = 0x2 - Pullup is ~12 KOhms PULL24K = 0x3 - Pullup is ~24 KOhms |
13:11 | PAD5FNCSEL | RW | Pad 5 function select M0SCL = 0x0 - Configure as the IOMSTR0 I2C SCL signal M0SCK = 0x1 - Configure as the IOMSTR0 SPI SCK signal UA0RTS = 0x2 - Configure as the UART0 RTS signal output GPIO5 = 0x3 - Configure as GPIO5 RSVD4 = 0x4 - Reserved EXTHFA = 0x5 - Configure as the External HFA input clock RSVD6 = 0x6 - Reserved CT8 = 0x7 - CTIMER connection 8 |
10 | PAD5STRNG | RW | Pad 5 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD5INPEN | RW | Pad 5 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD5PULL | RW | Pad 5 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:6 | RSVD | RO | RESERVED |
5:3 | PAD4FNCSEL | RW | Pad 4 function select UA0CTS = 0x0 - Configure as the UART0 CTS input signal SLINT = 0x1 - Configure as the IOSLAVE interrupt out signal NCE4 = 0x2 - IOM/SPI nCE group 4 GPIO4 = 0x3 - Configure as GPIO4 RSVD4 = 0x4 - Reserved UART0RX = 0x5 - Configure as the UART0 RX input CT17 = 0x6 - CTIMER connection 17 MSPI2 = 0x7 - MSPI data connection 2 |
2 | PAD4STRNG | RW | Pad 4 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD4INPEN | RW | Pad 4 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD4PULL | RW | Pad 4 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x40010008 |
This register controls the pad configuration controls for PAD11 through PAD8. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD11FNCSEL
0x3 |
PAD11STRNG
0x0 |
PAD11INPEN
0x0 |
PAD11PULL
0x0 |
RSVD
0x0 |
PAD10FNCSEL
0x3 |
PAD10STRNG
0x0 |
PAD10INPEN
0x0 |
PAD10PULL
0x0 |
PAD9RSEL
0x0 |
PAD9FNCSEL
0x3 |
PAD9STRNG
0x0 |
PAD9INPEN
0x0 |
PAD9PULL
0x0 |
PAD8RSEL
0x0 |
PAD8FNCSEL
0x3 |
PAD8STRNG
0x0 |
PAD8INPEN
0x0 |
PAD8PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:30 | RSVD | RO | RESERVED |
29:27 | PAD11FNCSEL | RW | Pad 11 function select ADCSE2 = 0x0 - Configure as the analog input for ADC single ended input 2 NCE11 = 0x1 - IOM/MSPI nCE group 11 CT31 = 0x2 - CTIMER connection 31 GPIO11 = 0x3 - Configure as GPIO11 SLINT = 0x4 - Configure as the IOSLAVE interrupt out signal UA1CTS = 0x5 - Configure as the UART1 CTS input signal UART0RX = 0x6 - Configure as the UART0 RX input signal PDM_DATA = 0x7 - Configure as the PDM Data input signal |
26 | PAD11STRNG | RW | Pad 11 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD11INPEN | RW | Pad 11 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD11PULL | RW | Pad 11 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:22 | RSVD | RO | RESERVED |
21:19 | PAD10FNCSEL | RW | Pad 10 function select RSVD0 = 0x0 - Reserved M1MOSI = 0x1 - Configure as the IOMSTR1 SPI MOSI signal NCE10 = 0x2 - IOM/MSPI nCE group 10 GPIO10 = 0x3 - Configure as GPIO10 PDMCLK = 0x4 - PDM serial clock out UA1RTS = 0x5 - Configure as the UART1 RTS output signal RSVD6 = 0x6 - Reserved RSVD7 = 0x7 - REserved |
18 | PAD10STRNG | RW | Pad 10 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD10INPEN | RW | Pad 10 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD10PULL | RW | Pad 10 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:14 | PAD9RSEL | RW | Pad 9 pullup resistor selection PULL1_5K = 0x0 - Pullup is ~1.5 KOhms PULL6K = 0x1 - Pullup is ~6 KOhms PULL12K = 0x2 - Pullup is ~12 KOhms PULL24K = 0x3 - Pullup is ~24 KOhms |
13:11 | PAD9FNCSEL | RW | Pad 9 function select M1SDAWIR3 = 0x0 - Configure as the IOMSTR1 I2C SDA or SPI WIR3 signal M1MISO = 0x1 - Configure as the IOMSTR1 SPI MISO signal NCE9 = 0x2 - IOM/MSPI nCE group 9 GPIO9 = 0x3 - Configure as GPIO9 SCCIO = 0x4 - SCARD data I/O connection RSVD5 = 0x5 - Reserved UART1RX = 0x6 - Configure as UART1 RX input signal RSVD7 = 0x7 - Reserved |
10 | PAD9STRNG | RW | Pad 9 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD9INPEN | RW | Pad 9 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD9PULL | RW | Pad 9 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:6 | PAD8RSEL | RW | Pad 8 pullup resistor selection. PULL1_5K = 0x0 - Pullup is ~1.5 KOhms PULL6K = 0x1 - Pullup is ~6 KOhms PULL12K = 0x2 - Pullup is ~12 KOhms PULL24K = 0x3 - Pullup is ~24 KOhms |
5:3 | PAD8FNCSEL | RW | Pad 8 function select M1SCL = 0x0 - Configure as the IOMSTR1 I2C SCL signal M1SCK = 0x1 - Configure as the IOMSTR1 SPI SCK signal NCE8 = 0x2 - IOM/MSPI nCE group 8 GPIO8 = 0x3 - Configure as GPIO8 SCCLK = 0x4 - SCARD serial clock output RSVD5 = 0x5 - Reserved UART1TX = 0x6 - Configure as the UART1 TX output signal RSVD7 = 0x7 - Reserved |
2 | PAD8STRNG | RW | Pad 8 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD8INPEN | RW | Pad 8 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD8PULL | RW | Pad 8 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x4001000C |
This register controls the pad configuration controls for PAD15 through PAD12. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD15FNCSEL
0x3 |
PAD15STRNG
0x0 |
PAD15INPEN
0x0 |
PAD15PULL
0x0 |
RSVD
0x0 |
PAD14FNCSEL
0x3 |
PAD14STRNG
0x0 |
PAD14INPEN
0x0 |
PAD14PULL
0x0 |
RSVD
0x0 |
PAD13FNCSEL
0x3 |
PAD13STRNG
0x0 |
PAD13INPEN
0x0 |
PAD13PULL
0x0 |
RSVD
0x0 |
PAD12FNCSEL
0x3 |
PAD12STRNG
0x0 |
PAD12INPEN
0x0 |
PAD12PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:30 | RSVD | RO | RESERVED |
29:27 | PAD15FNCSEL | RW | Pad 15 function select ADCD1N = 0x0 - Configure as the analog ADC differential pair 1 N input signal NCE15 = 0x1 - IOM/MSPI nCE group 15 UART1RX = 0x2 - Configure as the UART1 RX signal GPIO15 = 0x3 - Configure as GPIO15 PDMDATA = 0x4 - PDM serial data input EXTXT = 0x5 - Configure as the external XTAL oscillator input SWDIO = 0x6 - Configure as an alternate port for the SWDIO I/O signal SWO = 0x7 - Configure as an SWO (Serial Wire Trace output) |
26 | PAD15STRNG | RW | Pad 15 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD15INPEN | RW | Pad 15 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD15PULL | RW | Pad 15 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:22 | RSVD | RO | RESERVED |
21:19 | PAD14FNCSEL | RW | Pad 14 function select ADCD1P = 0x0 - Configure as the analog ADC differential pair 1 P input signal NCE14 = 0x1 - IOM/MSPI nCE group 14 UART1TX = 0x2 - Configure as the UART1 TX output signal GPIO14 = 0x3 - Configure as GPIO14 PDMCLK = 0x4 - PDM serial clock output EXTHFS = 0x5 - Configure as the External HFRC oscillator input select SWDCK = 0x6 - Configure as the alternate input for the SWDCK input signal 32kHzXT = 0x7 - Configure as the 32kHz crystal output signal |
18 | PAD14STRNG | RW | Pad 14 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD14INPEN | RW | Pad 14 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD14PULL | RW | Pad 14 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:14 | RSVD | RO | RESERVED |
13:11 | PAD13FNCSEL | RW | Pad 13 function select ADCD0PSE8 = 0x0 - Configure as the ADC Differential pair 0 P, or Single Ended input 8 analog input signal. Determination of the D0P vs SE8 usage is done when the particular channel is selected within the ADC module NCE13 = 0x1 - IOM/MSPI nCE group 13 CT2 = 0x2 - CTIMER connection 2 GPIO13 = 0x3 - Configure as GPIO13 I2SBCLK = 0x4 - I2C interface bit clock EXTHFB = 0x5 - Configure as the external HFRC oscillator input UA0RTS = 0x6 - Configure as the UART0 RTS signal output UART1RX = 0x7 - Configure as the UART1 RX input signal |
10 | PAD13STRNG | RW | Pad 13 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD13INPEN | RW | Pad 13 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD13PULL | RW | Pad 13 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:6 | RSVD | RO | RESERVED |
5:3 | PAD12FNCSEL | RW | Pad 12 function select ADCD0NSE9 = 0x0 - Configure as the ADC Differential pair 0 N, or Single Ended input 9 analog input signal. Determination of the D0N vs SE9 usage is done when the particular channel is selected within the ADC module NCE12 = 0x1 - IOM/MSPI nCE group 12 CT0 = 0x2 - CTIMER connection 0 GPIO12 = 0x3 - Configure as GPIO12 SLnCE = 0x4 - Configure as the IOSLAVE SPI nCE signal PDMCLK = 0x5 - PDM serial clock output UA0CTS = 0x6 - Configure as the UART0 CTS input signal UART1TX = 0x7 - Configure as the UART1 TX output signal |
2 | PAD12STRNG | RW | Pad 12 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD12INPEN | RW | Pad 12 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD12PULL | RW | Pad 12 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x40010010 |
This register controls the pad configuration controls for PAD19 through PAD16. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD19FNCSEL
0x3 |
PAD19STRNG
0x0 |
PAD19INPEN
0x0 |
PAD19PULL
0x0 |
RSVD
0x0 |
PAD18FNCSEL
0x3 |
PAD18STRNG
0x0 |
PAD18INPEN
0x0 |
PAD18PULL
0x0 |
RSVD
0x0 |
PAD17FNCSEL
0x3 |
PAD17STRNG
0x0 |
PAD17INPEN
0x0 |
PAD17PULL
0x0 |
RSVD
0x0 |
PAD16FNCSEL
0x3 |
PAD16STRNG
0x0 |
PAD16INPEN
0x0 |
PAD16PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:30 | RSVD | RO | RESERVED |
29:27 | PAD19FNCSEL | RW | Pad 19 function select CMPRF0 = 0x0 - Configure as the analog comparator reference 0 signal NCE19 = 0x1 - IOM/MSPI nCE group 19 CT6 = 0x2 - CTIMER conenction 6 GPIO19 = 0x3 - Configure as GPIO19 SCCLK = 0x4 - SCARD serial clock ANATEST1 = 0x5 - Configure as the ANATEST1 I/O signal UART1RX = 0x6 - Configure as the UART1 RX input signal I2SBCLK = 0x7 - Configure as the PDM I2S bit clock input signal |
26 | PAD19STRNG | RW | Pad 19 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD19INPEN | RW | Pad 19 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD19PULL | RW | Pad 19 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:22 | RSVD | RO | RESERVED |
21:19 | PAD18FNCSEL | RW | Pad 18 function select CMPIN1 = 0x0 - Configure as the analog comparator input 1 signal NCE18 = 0x1 - IOM/MSPI nCE group 18 CT4 = 0x2 - CTIMER connection 4 GPIO18 = 0x3 - Configure as GPIO18 UA0RTS = 0x4 - Configure as UART0 RTS output signal ANATEST2 = 0x5 - Configure as ANATEST2 I/O signal UART1TX = 0x6 - Configure as UART1 TX output signal SCCIO = 0x7 - SCARD data input/output connectin |
18 | PAD18STRNG | RW | Pad 18 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD18INPEN | RW | Pad 18 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD18PULL | RW | Pad 18 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:14 | RSVD | RO | RESERVED |
13:11 | PAD17FNCSEL | RW | Pad 17 function select CMPRF1 = 0x0 - Configure as the analog comparator reference signal 1 input signal NCE17 = 0x1 - IOM/MSPI nCE group 17 TRIG1 = 0x2 - Configure as the ADC Trigger 1 signal GPIO17 = 0x3 - Configure as GPIO17 SCCCLK = 0x4 - SCARD serial clock output RSVD = 0x5 - Reserved UART0RX = 0x6 - Configure as UART0 RX input signal UA1CTS = 0x7 - Configure as UART1 CTS input signal |
10 | PAD17STRNG | RW | Pad 17 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD17INPEN | RW | Pad 17 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD17PULL | RW | Pad 17 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:6 | RSVD | RO | RESERVED |
5:3 | PAD16FNCSEL | RW | Pad 16 function select ADCSE0 = 0x0 - Configure as the analog ADC single ended port 0 input signal NCE16 = 0x1 - IOM/MSPI nCE group 16 TRIG0 = 0x2 - Configure as the ADC Trigger 0 signal GPIO16 = 0x3 - Configure as GPIO16 SCCRST = 0x4 - SCARD reset output CMPIN0 = 0x5 - Configure as comparator input 0 signal UART0TX = 0x6 - Configure as UART0 TX output signal UA1RTS = 0x7 - Configure as UART1 RTS output signal |
2 | PAD16STRNG | RW | Pad 16 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD16INPEN | RW | Pad 16 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD16PULL | RW | Pad 16 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x40010014 |
This register controls the pad configuration controls for PAD23 through PAD20. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD23FNCSEL
0x3 |
PAD23STRNG
0x0 |
PAD23INPEN
0x0 |
PAD23PULL
0x0 |
RSVD
0x0 |
PAD22FNCSEL
0x3 |
PAD22STRNG
0x0 |
PAD22INPEN
0x0 |
PAD22PULL
0x0 |
RSVD
0x0 |
PAD21FNCSEL
0x0 |
PAD21STRNG
0x0 |
PAD21INPEN
0x1 |
PAD21PULL
0x0 |
RSVD
0x0 |
PAD20FNCSEL
0x0 |
PAD20STRNG
0x0 |
PAD20INPEN
0x1 |
PAD20PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:30 | RSVD | RO | RESERVED |
29:27 | PAD23FNCSEL | RW | Pad 23 function select UART0RX = 0x0 - Configure as the UART0 RX signal NCE23 = 0x1 - IOM/MSPI nCE group 23 CT14 = 0x2 - CTIMER connection 14 GPIO23 = 0x3 - Configure as GPIO23 I2SWCLK = 0x4 - I2S word clock input CMPOUT = 0x5 - Configure as voltage comparitor output MSPI3 = 0x6 - MSPI data connection 3 EXTXT = 0x7 - External XTAL osacillatgor input |
26 | PAD23STRNG | RW | Pad 23 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD23INPEN | RW | Pad 23 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD23PULL | RW | Pad 23 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:22 | RSVD | RO | RESERVED |
21:19 | PAD22FNCSEL | RW | Pad 22 function select UART0TX = 0x0 - Configure as the UART0 TX signal NCE22 = 0x1 - IOM/MSPI nCE group 22 CT12 = 0x2 - CTIMER connection 12 GPIO22 = 0x3 - Configure as GPIO22 PDM_CLK = 0x4 - Configure as the PDM CLK output EXTLF = 0x5 - External LFRC input MSPI0 = 0x6 - MSPI data connection 0 SWO = 0x7 - Configure as the serial trace data output signal |
18 | PAD22STRNG | RW | Pad 22 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD22INPEN | RW | Pad 22 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD22PULL | RW | Pad 22 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:14 | RSVD | RO | RESERVED |
13:11 | PAD21FNCSEL | RW | Pad 21 function select SWDIO = 0x0 - Configure as the serial wire debug data signal NCE21 = 0x1 - IOM/MSPI nCE group 21 RSVD = 0x2 - Reserved GPIO21 = 0x3 - Configure as GPIO21 UART0RX = 0x4 - Configure as UART0 RX input signal UART1RX = 0x5 - Configure as UART1 RX input signal I2SBCLK = 0x6 - I2S byte clock input UA1CTS = 0x7 - Configure as UART1 CTS input signal |
10 | PAD21STRNG | RW | Pad 21 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD21INPEN | RW | Pad 21 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD21PULL | RW | Pad 21 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:6 | RSVD | RO | RESERVED |
5:3 | PAD20FNCSEL | RW | Pad 20 function select SWDCK = 0x0 - Configure as the serial wire debug clock signal NCE20 = 0x1 - IOM/MSPI nCE group 20 RSVD = 0x2 - Reserved GPIO20 = 0x3 - Configure as GPIO20 UART0TX = 0x4 - Configure as UART0 TX output signal UART1TX = 0x5 - Configure as UART1 TX output signal I2SBCLK = 0x6 - I2S byte clock input UA1RTS = 0x7 - Configure as UART1 RTS output signal |
2 | PAD20STRNG | RW | Pad 20 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD20INPEN | RW | Pad 20 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD20PULL | RW | Pad 20 pulldown enable DIS = 0x0 - Pulldown disabled EN = 0x1 - Pulldown enabled |
Instance 0 Address: | 0x40010018 |
This register controls the pad configuration controls for PAD27 through PAD24. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PAD27RSEL
0x0 |
PAD27FNCSEL
0x3 |
PAD27STRNG
0x0 |
PAD27INPEN
0x0 |
PAD27PULL
0x0 |
RSVD
0x0 |
PAD26FNCSEL
0x3 |
PAD26STRNG
0x0 |
PAD26INPEN
0x0 |
PAD26PULL
0x0 |
PAD25RSEL
0x0 |
PAD25FNCSEL
0x3 |
PAD25STRNG
0x0 |
PAD25INPEN
0x0 |
PAD25PULL
0x0 |
RSVD
0x0 |
PAD24FNCSEL
0x3 |
PAD24STRNG
0x0 |
PAD24INPEN
0x0 |
PAD24PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:30 | PAD27RSEL | RW | Pad 27 pullup resistor selection. PULL1_5K = 0x0 - Pullup is ~1.5 KOhms PULL6K = 0x1 - Pullup is ~6 KOhms PULL12K = 0x2 - Pullup is ~12 KOhms PULL24K = 0x3 - Pullup is ~24 KOhms |
29:27 | PAD27FNCSEL | RW | Pad 27 function select UART0RX = 0x0 - Configure as UART0 RX input signal NCE27 = 0x1 - IOM/MSPI nCE group 27 CT5 = 0x2 - CTIMER connection 5 GPIO27 = 0x3 - Configure as GPIO27 M2SCL = 0x4 - Configure as I2C clock I/O signal from IOMSTR2 M2SCK = 0x5 - Configure as SPI clock output signal from IOMSTR2 RSVD6 = 0x6 - Reserved RSVD7 = 0x7 - Reserved |
26 | PAD27STRNG | RW | Pad 27 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD27INPEN | RW | Pad 27 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD27PULL | RW | Pad 27 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:22 | RSVD | RO | RESERVED |
21:19 | PAD26FNCSEL | RW | Pad 26 function select EXTHF = 0x0 - Configure as the external HFRC oscillator input NCE26 = 0x1 - IOM/MSPI nCE group 26 CT3 = 0x2 - CTIMER connection 3 GPIO26 = 0x3 - Configure as GPIO26 SCCRST = 0x4 - SCARD reset output MSPI1 = 0x5 - MSPI data connection 1 UART0TX = 0x6 - Configure as UART0 TX output signal UA1CTS = 0x7 - Configure as UART1 CTS input signal |
18 | PAD26STRNG | RW | Pad 26 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD26INPEN | RW | Pad 26 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD26PULL | RW | Pad 26 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:14 | PAD25RSEL | RW | Pad 25 pullup resistor selection. PULL1_5K = 0x0 - Pullup is ~1.5 KOhms PULL6K = 0x1 - Pullup is ~6 KOhms PULL12K = 0x2 - Pullup is ~12 KOhms PULL24K = 0x3 - Pullup is ~24 KOhms |
13:11 | PAD25FNCSEL | RW | Pad 25 function select UART1RX = 0x0 - Configure as UART1 RX input signal NCE25 = 0x1 - IOM/MSPI nCE group 25 CT1 = 0x2 - CTIMER connection 1 GPIO25 = 0x3 - Configure as GPIO25 M2SDAWIR3 = 0x4 - Configure as the IOMSTR2 I2C SDA or SPI WIR3 signal M2MISO = 0x5 - Configure as the IOMSTR2 SPI MISO input signal RSVD6 = 0x6 - Reserved RSVD7 = 0x7 - Reserved |
10 | PAD25STRNG | RW | Pad 25 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD25INPEN | RW | Pad 25 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD25PULL | RW | Pad 25 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:6 | RSVD | RO | RESERVED |
5:3 | PAD24FNCSEL | RW | Pad 24 function select UART1TX = 0x0 - Configure as UART1 TX output signal NCE24 = 0x1 - IOM/MSPI nCE group 24 MSPI8 = 0x2 - MSPI data connection 8 GPIO24 = 0x3 - Configure as GPIO24 UA0CTS = 0x4 - Configure as UART0 CTS input signal CT21 = 0x5 - CTIMER connection 21 32kHzXT = 0x6 - Configure as the 32kHz crystal output signal SWO = 0x7 - Configure as the serial trace data output signal |
2 | PAD24STRNG | RW | Pad 24 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD24INPEN | RW | Pad 24 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD24PULL | RW | Pad 24 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x4001001C |
This register controls the pad configuration controls for PAD31 through PAD28. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD31FNCSEL
0x3 |
PAD31STRNG
0x0 |
PAD31INPEN
0x0 |
PAD31PULL
0x0 |
RSVD
0x0 |
PAD30FNCSEL
0x3 |
PAD30STRNG
0x0 |
PAD30INPEN
0x0 |
PAD30PULL
0x0 |
RSVD
0x0 |
PAD29FNCSEL
0x3 |
PAD29STRNG
0x0 |
PAD29INPEN
0x0 |
PAD29PULL
0x0 |
RSVD
0x0 |
PAD28FNCSEL
0x3 |
PAD28STRNG
0x0 |
PAD28INPEN
0x0 |
PAD28PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:30 | RSVD | RO | RESERVED |
29:27 | PAD31FNCSEL | RW | Pad 31 function select ADCSE3 = 0x0 - Configure as the analog input for ADC single ended input 3 NCE31 = 0x1 - IOM/MSPI nCE group 31 CT13 = 0x2 - CTIMER connection 13 GPIO31 = 0x3 - Configure as GPIO31 UART0RX = 0x4 - Configure as the UART0 RX input signal SCCCLK = 0x5 - SCARD serial clock output RSVD = 0x6 - Reserved UA1RTS = 0x7 - Configure as UART1 RTS output signal |
26 | PAD31STRNG | RW | Pad 31 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD31INPEN | RW | Pad 31 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD31PULL | RW | Pad 31 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:22 | RSVD | RO | RESERVED |
21:19 | PAD30FNCSEL | RW | Pad 30 function select ANATEST1 = 0x0 - Configure as the ANATEST1 I/O signal NCE30 = 0x1 - IOM/MSPI nCE group 30 CT11 = 0x2 - CTIMER connection 11 GPIO30 = 0x3 - Configure as GPIO30 UART0TX = 0x4 - Configure as UART0 TX output signal UA1RTS = 0x5 - Configure as UART1 RTS output signal RSVD = 0x6 - Reserved I2S_DAT = 0x7 - Configure as the PDM I2S Data output signal |
18 | PAD30STRNG | RW | Pad 30 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD30INPEN | RW | Pad 30 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD30PULL | RW | Pad 30 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:14 | RSVD | RO | RESERVED |
13:11 | PAD29FNCSEL | RW | Pad 29 function select ADCSE1 = 0x0 - Configure as the analog input for ADC single ended input 1 NCE29 = 0x1 - IOM/MSPI nCE group 29 CT9 = 0x2 - CTIMER connection 9 GPIO29 = 0x3 - Configure as GPIO29 UA0CTS = 0x4 - Configure as the UART0 CTS input signal UA1CTS = 0x5 - Configure as the UART1 CTS input signal UART0RX = 0x6 - Configure as the UART0 RX input signal PDM_DATA = 0x7 - Configure as PDM DATA input |
10 | PAD29STRNG | RW | Pad 29 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD29INPEN | RW | Pad 29 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD29PULL | RW | Pad 29 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:6 | RSVD | RO | RESERVED |
5:3 | PAD28FNCSEL | RW | Pad 28 function select I2S_WCLK = 0x0 - Configure as the PDM I2S Word Clock input NCE28 = 0x1 - IOM/MSPI nCE group 28 CT7 = 0x2 - CTIMER connection 7 GPIO28 = 0x3 - Configure as GPIO28 RSVD4 = 0x4 - Reserved M2MOSI = 0x5 - Configure as the IOMSTR2 SPI MOSI output signal UART0TX = 0x6 - Configure as the UART0 TX output signal RSVD7 = 0x7 - Reserved |
2 | PAD28STRNG | RW | Pad 28 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD28INPEN | RW | Pad 28 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD28PULL | RW | Pad 28 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x40010020 |
This register controls the pad configuration controls for PAD35 through PAD32. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD35FNCSEL
0x3 |
PAD35STRNG
0x0 |
PAD35INPEN
0x0 |
PAD35PULL
0x0 |
RSVD
0x0 |
PAD34FNCSEL
0x3 |
PAD34STRNG
0x0 |
PAD34INPEN
0x0 |
PAD34PULL
0x0 |
RSVD
0x0 |
PAD33FNCSEL
0x3 |
PAD33STRNG
0x0 |
PAD33INPEN
0x0 |
PAD33PULL
0x0 |
RSVD
0x0 |
PAD32FNCSEL
0x3 |
PAD32STRNG
0x0 |
PAD32INPEN
0x0 |
PAD32PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:30 | RSVD | RO | RESERVED |
29:27 | PAD35FNCSEL | RW | Pad 35 function select ADCSE7 = 0x0 - Configure as the analog input for ADC single ended input 7 NCE35 = 0x1 - IOM/MSPI nCE group 35 UART1TX = 0x2 - Configure as the UART1 TX signal GPIO35 = 0x3 - Configure as GPIO35 I2SDAT = 0x4 - I2S serial data output CT27 = 0x5 - CTIMER connection 27 UA0RTS = 0x6 - Configure as the UART0 RTS output RSVD = 0x7 - Reserved |
26 | PAD35STRNG | RW | Pad 35 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD35INPEN | RW | Pad 35 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD35PULL | RW | Pad 35 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:22 | RSVD | RO | RESERVED |
21:19 | PAD34FNCSEL | RW | Pad 34 function select ADCSE6 = 0x0 - Configure as the analog input for ADC single ended input 6 NCE34 = 0x1 - IOM/MSPI nCE group 34 UA1RTS = 0x2 - Configure as the UART1 RTS output GPIO34 = 0x3 - Configure as GPIO34 CMPRF2 = 0x4 - Configure as the analog comparator reference 2 signal UA0RTS = 0x5 - Configure as the UART0 RTS output UART0RX = 0x6 - Configure as the UART0 RX input PDMDATA = 0x7 - PDM serial data input |
18 | PAD34STRNG | RW | Pad 34 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD34INPEN | RW | Pad 34 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD34PULL | RW | Pad 34 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:14 | RSVD | RO | RESERVED |
13:11 | PAD33FNCSEL | RW | Pad 33 function select ADCSE5 = 0x0 - Configure as the analog ADC single ended port 5 input signal NCE33 = 0x1 - IOM/MSPI nCE group 33 32kHzXT = 0x2 - Configure as the 32kHz crystal output signal GPIO33 = 0x3 - Configure as GPIO33 RSVD = 0x4 - Reserved UA0CTS = 0x5 - Configure as the UART0 CTS input CT23 = 0x6 - CTIMER connection 23 SWO = 0x7 - Configure as the serial trace data output signal |
10 | PAD33STRNG | RW | Pad 33 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD33INPEN | RW | Pad 33 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD33PULL | RW | Pad 33 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:6 | RSVD | RO | RESERVED |
5:3 | PAD32FNCSEL | RW | Pad 32 function select ADCSE4 = 0x0 - Configure as the analog input for ADC single ended input 4 NCE32 = 0x1 - IOM/MSPI nCE group 32 CT15 = 0x2 - CTIMER connection 15 GPIO32 = 0x3 - Configure as GPIO32 SCCIO = 0x4 - SCARD serial data input/output EXTLF = 0x5 - External input to the LFRC oscillator RSVD = 0x6 - Reserved UA1CTS = 0x7 - Configure as the UART1 CTS input |
2 | PAD32STRNG | RW | Pad 32 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD32INPEN | RW | Pad 32 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD32PULL | RW | Pad 32 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x40010024 |
This register controls the pad configuration controls for PAD39 through PAD36. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PAD39RSEL
0x0 |
PAD39FNCSEL
0x3 |
PAD39STRNG
0x0 |
PAD39INPEN
0x0 |
PAD39PULL
0x0 |
RSVD
0x0 |
PAD38FNCSEL
0x3 |
PAD38STRNG
0x0 |
PAD38INPEN
0x0 |
PAD38PULL
0x0 |
PAD37PWRDN
0x0 |
RSVD
0x0 |
PAD37FNCSEL
0x3 |
PAD37STRNG
0x0 |
PAD37INPEN
0x0 |
PAD37PULL
0x0 |
RSVD
0x0 |
PAD36PWRUP
0x0 |
PAD36FNCSEL
0x3 |
PAD36STRNG
0x0 |
PAD36INPEN
0x0 |
PAD36PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:30 | PAD39RSEL | RW | Pad 39 pullup resistor selection. PULL1_5K = 0x0 - Pullup is ~1.5 KOhms PULL6K = 0x1 - Pullup is ~6 KOhms PULL12K = 0x2 - Pullup is ~12 KOhms PULL24K = 0x3 - Pullup is ~24 KOhms |
29:27 | PAD39FNCSEL | RW | Pad 39 function select UART0TX = 0x0 - Configure as the UART0 TX output signal UART1TX = 0x1 - Configure as the UART1 TX output signal CT25 = 0x2 - CTIMER connection 25 GPIO39 = 0x3 - Configure as GPIO39 M4SCL = 0x4 - Configure as the IOMSTR4 I2C SCL signal M4SCK = 0x5 - Configure as the IOMSTR4 SPI SCK signal RSVD6 = 0x6 - Reserved RSVD7 = 0x7 - Reserved |
26 | PAD39STRNG | RW | Pad 39 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD39INPEN | RW | Pad 39 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD39PULL | RW | Pad 39 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:22 | RSVD | RO | RESERVED |
21:19 | PAD38FNCSEL | RW | Pad 38 function select TRIG3 = 0x0 - Configure as the ADC Trigger 3 signal NCE38 = 0x1 - IOM/MSPI nCE group 38 UA0CTS = 0x2 - Configure as the UART0 CTS signal GPIO38 = 0x3 - Configure as GPIO38 RSVD4 = 0x4 - Reserved M3MOSI = 0x5 - Configure as the IOMSTR3 SPI MOSI output signal UART1RX = 0x6 - Configure as the UART1 RX input signal RSVD7 = 0x7 - Reserved |
18 | PAD38STRNG | RW | Pad 38 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD38INPEN | RW | Pad 38 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD38PULL | RW | Pad 38 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15 | PAD37PWRDN | RW | Pad 37 VSS power switch enable DIS = 0x0 - Power switch disabled EN = 0x1 - Power switch enabled (switch to GND) |
14 | RSVD | RO | RESERVED |
13:11 | PAD37FNCSEL | RW | Pad 37 function select TRIG2 = 0x0 - Configure as the ADC Trigger 2 signal NCE37 = 0x1 - IOM/MSPI nCE group 37 UA0RTS = 0x2 - Configure as the UART0 RTS output signal GPIO37 = 0x3 - Configure as GPIO37 SCCIO = 0x4 - SCARD serial data input/output UART1TX = 0x5 - Configure as the UART1 TX output signal PDMCLK = 0x6 - Configure as the PDM CLK output signal CT29 = 0x7 - CTIMER connection 29 |
10 | PAD37STRNG | RW | Pad 37 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD37INPEN | RW | Pad 37 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD37PULL | RW | Pad 37 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7 | RSVD | RO | RESERVED |
6 | PAD36PWRUP | RW | Pad 36 VDD power switch enable DIS = 0x0 - Power switch disabled EN = 0x1 - Power switch enabled (switched to VDD) |
5:3 | PAD36FNCSEL | RW | Pad 36 function select TRIG1 = 0x0 - Configure as the ADC Trigger 1 signal NCE36 = 0x1 - IOM/MSPI nCE group 36 UART1RX = 0x2 - Configure as the UART1 RX input signal GPIO36 = 0x3 - Configure as GPIO36 32kHzXT = 0x4 - Configure as the 32kHz output clock from the crystal UA1CTS = 0x5 - Configure as the UART1 CTS input signal UA0CTS = 0x6 - Configure as the UART0 CTS input signal PDMDATA = 0x7 - PDM serial data input |
2 | PAD36STRNG | RW | Pad 36 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD36INPEN | RW | Pad 36 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD36PULL | RW | Pad 36 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x40010028 |
This register controls the pad configuration controls for PAD43 through PAD40. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PAD43RSEL
0x0 |
PAD43FNCSEL
0x3 |
PAD43STRNG
0x0 |
PAD43INPEN
0x0 |
PAD43PULL
0x0 |
PAD42RSEL
0x0 |
PAD42FNCSEL
0x3 |
PAD42STRNG
0x0 |
PAD42INPEN
0x0 |
PAD42PULL
0x0 |
PAD41PWRDN
0x0 |
RSVD
0x0 |
PAD41FNCSEL
0x3 |
PAD41STRNG
0x0 |
PAD41INPEN
0x0 |
PAD41PULL
0x0 |
PAD40RSEL
0x0 |
PAD40FNCSEL
0x3 |
PAD40STRNG
0x0 |
PAD40INPEN
0x0 |
PAD40PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:30 | PAD43RSEL | RW | Pad 43 pullup resistor selection. PULL1_5K = 0x0 - Pullup is ~1.5 KOhms PULL6K = 0x1 - Pullup is ~6 KOhms PULL12K = 0x2 - Pullup is ~12 KOhms PULL24K = 0x3 - Pullup is ~24 KOhms |
29:27 | PAD43FNCSEL | RW | Pad 43 function select UART1RX = 0x0 - Configure as the UART1 RX input signal NCE43 = 0x1 - IOM/MSPI nCE group 43 CT18 = 0x2 - CTIMER connection 18 GPIO43 = 0x3 - Configure as GPIO43 M3SDAWIR3 = 0x4 - Configure as the IOMSTR3 I2C SDA or SPI WIR3 signal M3MISO = 0x5 - Configure as the IOMSTR3 SPI MISO signal RSVD6 = 0x6 - Reserved RSVD7 = 0x7 - Reserved |
26 | PAD43STRNG | RW | Pad 43 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD43INPEN | RW | Pad 43 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD43PULL | RW | Pad 43 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:22 | PAD42RSEL | RW | Pad 42 pullup resistor selection. PULL1_5K = 0x0 - Pullup is ~1.5 KOhms PULL6K = 0x1 - Pullup is ~6 KOhms PULL12K = 0x2 - Pullup is ~12 KOhms PULL24K = 0x3 - Pullup is ~24 KOhms |
21:19 | PAD42FNCSEL | RW | Pad 42 function select UART1TX = 0x0 - Configure as the UART1 TX output signal NCE42 = 0x1 - IOM/MSPI nCE group 42 CT16 = 0x2 - CTIMER connection 16 GPIO42 = 0x3 - Configure as GPIO42 M3SCL = 0x4 - Configure as the IOMSTR3 I2C SCL clock I/O signal M3SCK = 0x5 - Configure as the IOMSTR3 SPI SCK output RSVD6 = 0x6 - Reserved RSVD7 = 0x7 - Reserved |
18 | PAD42STRNG | RW | Pad 42 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD42INPEN | RW | Pad 42 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD42PULL | RW | Pad 42 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15 | PAD41PWRDN | RW | Pad 41 power switch enable DIS = 0x0 - Power switch disabled EN = 0x1 - Power switch enabled (Switch pad to VSS) |
14 | RSVD | RO | RESERVED |
13:11 | PAD41FNCSEL | RW | Pad 41 function select NCE41 = 0x0 - IOM/MSPI nCE group 41 RSVD = 0x1 - Reserved SWO = 0x2 - Configure as the serial wire debug SWO signal GPIO41 = 0x3 - Configure as GPIO41 I2SWCLK = 0x4 - I2S word clock input UA1RTS = 0x5 - Configure as the UART1 RTS output signal UART0TX = 0x6 - Configure as the UART0 TX output signal UA0RTS = 0x7 - Configure as the UART0 RTS output signal |
10 | PAD41STRNG | RW | Pad 41 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD41INPEN | RW | Pad 41 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD41PULL | RW | Pad 41 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:6 | PAD40RSEL | RW | Pad 40 pullup resistor selection. PULL1_5K = 0x0 - Pullup is ~1.5 KOhms PULL6K = 0x1 - Pullup is ~6 KOhms PULL12K = 0x2 - Pullup is ~12 KOhms PULL24K = 0x3 - Pullup is ~24 KOhms |
5:3 | PAD40FNCSEL | RW | Pad 40 function select UART0RX = 0x0 - Configure as the UART0 RX input signal UART1RX = 0x1 - Configure as the UART1 RX input signal TRIG0 = 0x2 - Configure as the ADC Trigger 0 signal GPIO40 = 0x3 - Configure as GPIO40 M4SDAWIR3 = 0x4 - Configure as the IOMSTR4 I2C SDA or SPI WIR3 signal M4MISO = 0x5 - Configure as the IOMSTR4 SPI MISO input signal RSVD6 = 0x6 - Reserved RSVD7 = 0x7 - Reserved |
2 | PAD40STRNG | RW | Pad 40 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD40INPEN | RW | Pad 40 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD40PULL | RW | Pad 40 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x4001002C |
This register controls the pad configuration controls for PAD47 through PAD44. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD47FNCSEL
0x3 |
PAD47STRNG
0x0 |
PAD47INPEN
0x0 |
PAD47PULL
0x0 |
RSVD
0x0 |
PAD46FNCSEL
0x3 |
PAD46STRNG
0x0 |
PAD46INPEN
0x0 |
PAD46PULL
0x0 |
RSVD
0x0 |
PAD45FNCSEL
0x3 |
PAD45STRNG
0x0 |
PAD45INPEN
0x0 |
PAD45PULL
0x0 |
RSVD
0x0 |
PAD44FNCSEL
0x3 |
PAD44STRNG
0x0 |
PAD44INPEN
0x0 |
PAD44PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:30 | RSVD | RO | RESERVED |
29:27 | PAD47FNCSEL | RW | Pad 47 function select 32kHzXT = 0x0 - Configure as the 32kHz output clock from the crystal NCE47 = 0x1 - IOM/MSPI nCE group 47 CT26 = 0x2 - CTIMER connection 26 GPIO47 = 0x3 - Configure as GPIO47 RSVD4 = 0x4 - Reserved M5MOSI = 0x5 - Configure as the IOMSTR5 SPI MOSI output signal UART1RX = 0x6 - Configure as the UART1 RX input signal RSVD7 = 0x7 - Reserved |
26 | PAD47STRNG | RW | Pad 47 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD47INPEN | RW | Pad 47 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD47PULL | RW | Pad 47 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:22 | RSVD | RO | RESERVED |
21:19 | PAD46FNCSEL | RW | Pad 46 function select 32khz_XT = 0x0 - Configure as the 32kHz output clock from the crystal NCE46 = 0x1 - IOM/MSPI nCE group 46 CT24 = 0x2 - CTIMER connection 24 GPIO46 = 0x3 - Configure as GPIO46 SCCRST = 0x4 - SCARD reset output PDMCLK = 0x5 - PDM serial clock output UART1TX = 0x6 - Configure as the UART1 TX output signal SWO = 0x7 - Configure as the serial wire debug SWO signal |
18 | PAD46STRNG | RW | Pad 46 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD46INPEN | RW | Pad 46 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD46PULL | RW | Pad 46 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:14 | RSVD | RO | RESERVED |
13:11 | PAD45FNCSEL | RW | Pad 45 function select UA1CTS = 0x0 - Configure as the UART1 CTS input signal NCE45 = 0x1 - IOM/MSPI nCE group 45 CT22 = 0x2 - CTIMER connection 22 GPIO45 = 0x3 - Configure as GPIO45 I2SDAT = 0x4 - I2S serial data output PDMDATA = 0x5 - PDM serial data input UART0RX = 0x6 - Configure as the SPI channel 5 nCE signal from IOMSTR5 SWO = 0x7 - Configure as the serial wire debug SWO signal |
10 | PAD45STRNG | RW | Pad 45 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD45INPEN | RW | Pad 45 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD45PULL | RW | Pad 45 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:6 | RSVD | RO | RESERVED |
5:3 | PAD44FNCSEL | RW | Pad 44 function select UA1RTS = 0x0 - Configure as the UART1 RTS output signal NCE44 = 0x1 - IOM/MSPI nCE group 44 CT20 = 0x2 - CTIMER connection 20 GPIO44 = 0x3 - Configure as GPIO44 RSVD4 = 0x4 - Reserved M4MOSI = 0x5 - Configure as the IOMSTR4 SPI MOSI signal M5nCE6 = 0x6 - Configure as the SPI channel 6 nCE signal from IOMSTR5 RSVD = 0x7 - Reserved |
2 | PAD44STRNG | RW | Pad 44 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD44INPEN | RW | Pad 44 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD44PULL | RW | Pad 44 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x40010030 |
This register controls the pad configuration controls for PAD49 through PAD48. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD49RSEL
0x0 |
PAD49FNCSEL
0x3 |
PAD49STRNG
0x0 |
PAD49INPEN
0x0 |
PAD49PULL
0x0 |
PAD48RSEL
0x0 |
PAD48FNCSEL
0x3 |
PAD48STRNG
0x0 |
PAD48INPEN
0x0 |
PAD48PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:16 | RSVD | RO | RESERVED |
15:14 | PAD49RSEL | RW | Pad 49 pullup resistor selection. PULL1_5K = 0x0 - Pullup is ~1.5 KOhms PULL6K = 0x1 - Pullup is ~6 KOhms PULL12K = 0x2 - Pullup is ~12 KOhms PULL24K = 0x3 - Pullup is ~24 KOhms |
13:11 | PAD49FNCSEL | RW | Pad 49 function select UART0RX = 0x0 - Configure as the UART0 RX input signal NCE49 = 0x1 - IOM/MSPPI nCE group 49 CT30 = 0x2 - CTIMER connection 30 GPIO49 = 0x3 - Configure as GPIO49 M5SDAWIR3 = 0x4 - Configure as the IOMSTR5 I2C SDA or SPI WIR3 signal M5MISO = 0x5 - Configure as the IOMSTR5 SPI MISO input signal RSVD6 = 0x6 - Reserved RSVD7 = 0x7 - Reserved |
10 | PAD49STRNG | RW | Pad 49 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD49INPEN | RW | Pad 49 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD49PULL | RW | Pad 49 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:6 | PAD48RSEL | RW | Pad 48 pullup resistor selection. PULL1_5K = 0x0 - Pullup is ~1.5 KOhms PULL6K = 0x1 - Pullup is ~6 KOhms PULL12K = 0x2 - Pullup is ~12 KOhms PULL24K = 0x3 - Pullup is ~24 KOhms |
5:3 | PAD48FNCSEL | RW | Pad 48 function select UART0TX = 0x0 - Configure as the UART0 TX output signal NCE48 = 0x1 - IOM/MSPI nCE group 48 CT28 = 0x2 - CTIMER conenction 28 GPIO48 = 0x3 - Configure as GPIO48 M5SCL = 0x4 - Configure as the IOMSTR5 I2C SCL clock I/O signal M5SCK = 0x5 - Configure as the IOMSTR5 SPI SCK output RSVD6 = 0x6 - Reserved RSVD7 = 0x7 - Reserved |
2 | PAD48STRNG | RW | Pad 48 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD48INPEN | RW | Pad 48 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD48PULL | RW | Pad 48 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x40010040 |
GPIO configuration controls for GPIO[7:0]. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO7INTD
0x0 |
GPIO7OUTCFG
0x0 |
GPIO7INCFG
0x0 |
GPIO6INTD
0x0 |
GPIO6OUTCFG
0x0 |
GPIO6INCFG
0x0 |
GPIO5INTD
0x0 |
GPIO5OUTCFG
0x0 |
GPIO5INCFG
0x0 |
GPIO4INTD
0x0 |
GPIO4OUTCFG
0x0 |
GPIO4INCFG
0x0 |
GPIO3INTD
0x0 |
GPIO3OUTCFG
0x0 |
GPIO3INCFG
0x0 |
GPIO2INTD
0x0 |
GPIO2OUTCFG
0x0 |
GPIO2INCFG
0x0 |
GPIO1INTD
0x0 |
GPIO1OUTCFG
0x0 |
GPIO1INCFG
0x0 |
GPIO0INTD
0x0 |
GPIO0OUTCFG
0x0 |
GPIO0INCFG
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO7INTD | RW | GPIO7 interrupt direction, nCE polarity. nCELOW = 0x0 - FNCSEL = 0x0 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x0 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x0, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x0, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x0, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x0, INCFG = 0 - Interrupt on high to low GPIO transition |
30:29 | GPIO7OUTCFG | RW | GPIO7 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE1 = 0x0 - FNCSEL = 0x0 - IOM3 nCE, Channel 1 M4nCE1 = 0x1 - FNCSEL = 0x0 - IOM4 nCE, Channel 1 M5nCE1 = 0x2 - FNCSEL = 0x0 - IOM5 nCE, Channel 1 MSPInCE0 = 0x3 - FNCSEL = 0x0 - MSPI nCE, Channel 0 |
28 | GPIO7INCFG | RW | GPIO7 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
27 | GPIO6INTD | RW | GPIO6 interrupt direction. INTDIS = 0x0 - INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - INCFG = 0 - Interrupt on high to low GPIO transition |
26:25 | GPIO6OUTCFG | RW | GPIO6 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state |
24 | GPIO6INCFG | RW | GPIO6 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
23 | GPIO5INTD | RW | GPIO5 interrupt direction. INTDIS = 0x0 - INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - INCFG = 0 - Interrupt on high to low GPIO transition |
22:21 | GPIO5OUTCFG | RW | GPIO5 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state |
20 | GPIO5INCFG | RW | GPIO5 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
19 | GPIO4INTD | RW | GPIO4 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x2 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x2 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x2, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x2, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x2, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x2, INCFG = 0 - Interrupt on high to low GPIO transition |
18:17 | GPIO4OUTCFG | RW | GPIO4 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE1 = 0x0 - FNCSEL = 0x2 - IOM3 nCE, Channel 1 M4nCE1 = 0x1 - FNCSEL = 0x2 - IOM4 nCE, Channel 1 M5nCE1 = 0x2 - FNCSEL = 0x2 - IOM5 nCE, Channel 1 M1nCE1 = 0x3 - FNCSEL = 0x2 - IOM1 nCE, Channel 1 |
16 | GPIO4INCFG | RW | GPIO4 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
15 | GPIO3INTD | RW | GPIO3 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x2 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x2 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x2, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x2, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x2, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x2, INCFG = 0 - Interrupt on high to low GPIO transition |
14:13 | GPIO3OUTCFG | RW | GPIO3 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE0 = 0x0 - FNCSEL = 0x2 - IOM3 nCE, Channel 0 M4nCE0 = 0x1 - FNCSEL = 0x2 - IOM4 nCE, Channel 0 M5nCE0 = 0x2 - FNCSEL = 0x2 - IOM5 nCE, Channel 0 M2nCE0 = 0x3 - FNCSEL = 0x2 - IOM2 nCE, Channel 0 |
12 | GPIO3INCFG | RW | GPIO3 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
11 | GPIO2INTD | RW | GPIO2 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x7 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x7 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x7, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x7, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x7, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x7, INCFG = 0 - Interrupt on high to low GPIO transition |
10:9 | GPIO2OUTCFG | RW | GPIO2 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE3 = 0x0 - FNCSEL = 0x7 - IOM3 nCE, Channel 3 M4nCE3 = 0x1 - FNCSEL = 0x7 - IOM4 nCE, Channel 3 M5nCE3 = 0x2 - FNCSEL = 0x7 - IOM5 nCE, Channel 3 M2nCE1 = 0x3 - FNCSEL = 0x7 - IOM2 nCE, Channel 1 |
8 | GPIO2INCFG | RW | GPIO2 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
7 | GPIO1INTD | RW | GPIO1 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x7 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x7 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x7, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x7, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x7, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x7, INCFG = 0 - Interrupt on high to low GPIO transition |
6:5 | GPIO1OUTCFG | RW | GPIO1 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE2 = 0x0 - FNCSEL = 0x7 - IOM0 nCE, Channel 2 M1nCE2 = 0x1 - FNCSEL = 0x7 - IOM1 nCE, Channel 2 M2nCE2 = 0x2 - FNCSEL = 0x7 - IOM2 nCE, Channel 2 MSPInCE0 = 0x3 - FNCSEL = 0x7 - MSPI nCE, Channel 0 |
4 | GPIO1INCFG | RW | GPIO1 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
3 | GPIO0INTD | RW | GPIO0 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x7 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x7 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x7, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x7, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x7, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x7, INCFG = 0 - Interrupt on high to low GPIO transition |
2:1 | GPIO0OUTCFG | RW | GPIO0 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE2 = 0x0 - FNCSEL = 0x7 - IOM3 nCE, Channel 2 M4nCE2 = 0x1 - FNCSEL = 0x7 - IOM4 nCE, Channel 2 M5nCE2 = 0x2 - FNCSEL = 0x7 - IOM5 nCE, Channel 2 M1nCE3 = 0x3 - FNCSEL = 0x7 - IOM1 nCE, Channel 3 |
0 | GPIO0INCFG | RW | GPIO0 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
Instance 0 Address: | 0x40010044 |
GPIO configuration controls for GPIO[15:8]. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO15INTD
0x0 |
GPIO15OUTCFG
0x0 |
GPIO15INCFG
0x0 |
GPIO14INTD
0x0 |
GPIO14OUTCFG
0x0 |
GPIO14INCFG
0x0 |
GPIO13INTD
0x0 |
GPIO13OUTCFG
0x0 |
GPIO13INCFG
0x0 |
GPIO12INTD
0x0 |
GPIO12OUTCFG
0x0 |
GPIO12INCFG
0x0 |
GPIO11INTD
0x0 |
GPIO11OUTCFG
0x0 |
GPIO11INCFG
0x0 |
GPIO10INTD
0x0 |
GPIO10OUTCFG
0x0 |
GPIO10INCFG
0x0 |
GPIO9INTD
0x0 |
GPIO9OUTCFG
0x0 |
GPIO9INCFG
0x0 |
GPIO8INTD
0x0 |
GPIO8OUTCFG
0x0 |
GPIO8INCFG
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO15INTD | RW | GPIO15 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
30:29 | GPIO15OUTCFG | RW | GPIO15 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE3 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 3 M1nCE3 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 3 M2nCE3 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 3 MSPInCE0 = 0x3 - FNCSEL = 0x1 - MSPI nCE, Channel 0 |
28 | GPIO15INCFG | RW | GPIO15 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
27 | GPIO14INTD | RW | GPIO14 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
26:25 | GPIO14OUTCFG | RW | GPIO14 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE2 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 2 M1nCE2 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 2 M2nCE2 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 2 M4nCE2 = 0x3 - FNCSEL = 0x1 - IOM4 nCE, Channel 2 |
24 | GPIO14INCFG | RW | GPIO14 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
23 | GPIO13INTD | RW | GPIO13 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
22:21 | GPIO13OUTCFG | RW | GPIO13 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE1 = 0x0 - FNCSEL = 0x1 - IOM3 nCE, Channel 1 M4nCE1 = 0x1 - FNCSEL = 0x1 - IOM4 nCE, Channel 1 M5nCE1 = 0x2 - FNCSEL = 0x1 - IOM5 nCE, Channel 1 M0nCE1 = 0x3 - FNCSEL = 0x1 - IOM0 nCE, Channel 1 |
20 | GPIO13INCFG | RW | GPIO13 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
19 | GPIO12INTD | RW | GPIO12 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
18:17 | GPIO12OUTCFG | RW | GPIO12 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE0 = 0x0 - FNCSEL = 0x1 - IOM3 nCE, Channel 0 M4nCE0 = 0x1 - FNCSEL = 0x1 - IOM4 nCE, Channel 0 M5nCE0 = 0x2 - FNCSEL = 0x1 - IOM5 nCE, Channel 0 MSPInCE1 = 0x3 - FNCSEL = 0x1 - MPSI nCE, Channel 1 |
16 | GPIO12INCFG | RW | GPIO12 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
15 | GPIO11INTD | RW | GPIO11 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
14:13 | GPIO11OUTCFG | RW | GPIO11 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE0 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 0 M1nCE0 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 0 M2nCE0 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 0 M3nCE0 = 0x3 - FNCSEL = 0x1 - IOM3 nCE, Channel 0 |
12 | GPIO11INCFG | RW | GPIO11 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
11 | GPIO10INTD | RW | GPIO10 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x2 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x2 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x2, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x2, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x2, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x2, INCFG = 0 - Interrupt on high to low GPIO transition |
10:9 | GPIO10OUTCFG | RW | GPIO10 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE2 = 0x0 - FNCSEL = 0x1 - IOM3 nCE, Channel 2 M4nCE2 = 0x1 - FNCSEL = 0x1 - IOM4 nCE, Channel 2 M5nCE2 = 0x2 - FNCSEL = 0x1 - IOM5 nCE, Channel 2 MSPInCE0 = 0x3 - FNCSEL = 0x1 - MPSI nCE, Channel 0 |
8 | GPIO10INCFG | RW | GPIO10 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
7 | GPIO9INTD | RW | GPIO9 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x2 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x2 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x2, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x2, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x2, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x2, INCFG = 0 - Interrupt on high to low GPIO transition |
6:5 | GPIO9OUTCFG | RW | GPIO9 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE3 = 0x0 - FNCSEL = 0x1 - IOM3 nCE, Channel 3 M4nCE3 = 0x1 - FNCSEL = 0x1 - IOM4 nCE, Channel 3 M5nCE3 = 0x2 - FNCSEL = 0x1 - IOM5 nCE, Channel 3 M2nCE3 = 0x3 - FNCSEL = 0x1 - IOM2 nCE, Channel 3 |
4 | GPIO9INCFG | RW | GPIO9 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
3 | GPIO8INTD | RW | GPIO8 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x2 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x2 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x2, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x2, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x2, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x2, INCFG = 0 - Interrupt on high to low GPIO transition |
2:1 | GPIO8OUTCFG | RW | GPIO8 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE0 = 0x0 - FNCSEL = 0x1 - IOM3 nCE, Channel 0 M4nCE0 = 0x1 - FNCSEL = 0x1 - IOM4 nCE, Channel 0 M5nCE0 = 0x2 - FNCSEL = 0x1 - IOM5 nCE, Channel 0 M0nCE0 = 0x3 - FNCSEL = 0x1 - IOM0 nCE, Channel 0 |
0 | GPIO8INCFG | RW | GPIO8 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
Instance 0 Address: | 0x40010048 |
GPIO configuration controls for GPIO[23:16]. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO23INTD
0x0 |
GPIO23OUTCFG
0x0 |
GPIO23INCFG
0x0 |
GPIO22INTD
0x0 |
GPIO22OUTCFG
0x0 |
GPIO22INCFG
0x0 |
GPIO21INTD
0x0 |
GPIO21OUTCFG
0x0 |
GPIO21INCFG
0x1 |
GPIO20INTD
0x0 |
GPIO20OUTCFG
0x0 |
GPIO20INCFG
0x1 |
GPIO19INTD
0x0 |
GPIO19OUTCFG
0x0 |
GPIO19INCFG
0x0 |
GPIO18INTD
0x0 |
GPIO18OUTCFG
0x0 |
GPIO18INCFG
0x0 |
GPIO17INTD
0x0 |
GPIO17OUTCFG
0x0 |
GPIO17INCFG
0x0 |
GPIO16INTD
0x0 |
GPIO16OUTCFG
0x0 |
GPIO16INCFG
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO23INTD | RW | GPIO23 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
30:29 | GPIO23OUTCFG | RW | GPIO23 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE0 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 0 M1nCE0 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 0 M2nCE0 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 0 M4nCE0 = 0x3 - FNCSEL = 0x1 - IOM4 nCE, Channel 0 |
28 | GPIO23INCFG | RW | GPIO23 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
27 | GPIO22INTD | RW | GPIO22 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
26:25 | GPIO22OUTCFG | RW | GPIO22 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE3 = 0x0 - FNCSEL = 0x1 - IOM3 nCE, Channel 3 M4nCE3 = 0x1 - FNCSEL = 0x1 - IOM4 nCE, Channel 3 M5nCE3 = 0x2 - FNCSEL = 0x1 - IOM5 nCE, Channel 3 M0nCE3 = 0x3 - FNCSEL = 0x1 - IOM0 nCE, Channel 3 |
24 | GPIO22INCFG | RW | GPIO22 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
23 | GPIO21INTD | RW | GPIO21 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
22:21 | GPIO21OUTCFG | RW | GPIO21 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE2 = 0x0 - FNCSEL = 0x1 - IOM3 nCE, Channel 2 M4nCE2 = 0x1 - FNCSEL = 0x1 - IOM4 nCE, Channel 2 M5nCE2 = 0x2 - FNCSEL = 0x1 - IOM5 nCE, Channel 2 M2nCE2 = 0x3 - FNCSEL = 0x1 - IOM2 nCE, Channel 2 |
20 | GPIO21INCFG | RW | GPIO21 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
19 | GPIO20INTD | RW | GPIO20 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
18:17 | GPIO20OUTCFG | RW | GPIO20 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE1 = 0x0 - FNCSEL = 0x1 - IOM3 nCE, Channel 1 M4nCE1 = 0x1 - FNCSEL = 0x1 - IOM4 nCE, Channel 1 M5nCE1 = 0x2 - FNCSEL = 0x1 - IOM5 nCE, Channel 1 M2nCE1 = 0x3 - FNCSEL = 0x1 - IOM2 nCE, Channel 1 |
16 | GPIO20INCFG | RW | GPIO20 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
15 | GPIO19INTD | RW | GPIO19 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
14:13 | GPIO19OUTCFG | RW | GPIO19 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE3 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 3 M1nCE3 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 3 M2nCE3 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 3 MSPInCE0 = 0x3 - FNCSEL = 0x1 - MSPI nCE, Channel 0 |
12 | GPIO19INCFG | RW | GPIO19 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
11 | GPIO18INTD | RW | GPIO18 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
10:9 | GPIO18OUTCFG | RW | GPIO18 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE2 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 2 M1nCE2 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 2 M2nCE2 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 2 M3nCE2 = 0x3 - FNCSEL = 0x1 - IOM3 nCE, Channel 2 |
8 | GPIO18INCFG | RW | GPIO18 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
7 | GPIO17INTD | RW | GPIO17 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
6:5 | GPIO17OUTCFG | RW | GPIO17 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE1 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 1 M1nCE1 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 1 M2nCE1 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 1 M4nCE1 = 0x3 - FNCSEL = 0x1 - IOM4 nCE, Channel 1 |
4 | GPIO17INCFG | RW | GPIO17 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
3 | GPIO16INTD | RW | GPIO16 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
2:1 | GPIO16OUTCFG | RW | GPIO16 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE0 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 0 M1nCE0 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 0 M2nCE0 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 0 M5nCE0 = 0x3 - FNCSEL = 0x1 - IOM5 nCE, Channel 0 |
0 | GPIO16INCFG | RW | GPIO16 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
Instance 0 Address: | 0x4001004C |
GPIO configuration controls for GPIO[31:24]. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO31INTD
0x0 |
GPIO31OUTCFG
0x0 |
GPIO31INCFG
0x0 |
GPIO30INTD
0x0 |
GPIO30OUTCFG
0x0 |
GPIO30INCFG
0x0 |
GPIO29INTD
0x0 |
GPIO29OUTCFG
0x0 |
GPIO29INCFG
0x0 |
GPIO28INTD
0x0 |
GPIO28OUTCFG
0x0 |
GPIO28INCFG
0x0 |
GPIO27INTD
0x0 |
GPIO27OUTCFG
0x0 |
GPIO27INCFG
0x0 |
GPIO26INTD
0x0 |
GPIO26OUTCFG
0x0 |
GPIO26INCFG
0x0 |
GPIO25INTD
0x0 |
GPIO25OUTCFG
0x0 |
GPIO25INCFG
0x0 |
GPIO24INTD
0x0 |
GPIO24OUTCFG
0x0 |
GPIO24INCFG
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO31INTD | RW | GPIO31 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
30:29 | GPIO31OUTCFG | RW | GPIO31 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE0 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 0 M1nCE0 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 0 M2nCE0 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 0 M4nCE0 = 0x3 - FNCSEL = 0x1 - IOM4 nCE, Channel 0 |
28 | GPIO31INCFG | RW | GPIO31 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
27 | GPIO30INTD | RW | GPIO30 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
26:25 | GPIO30OUTCFG | RW | GPIO30 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE3 = 0x0 - FNCSEL = 0x1 - IOM3 nCE, Channel 3 M4nCE3 = 0x1 - FNCSEL = 0x1 - IOM4 nCE, Channel 3 M5nCE3 = 0x2 - FNCSEL = 0x1 - IOM5 nCE, Channel 3 M0nCE3 = 0x3 - FNCSEL = 0x1 - IOM0 nCE, Channel 3 |
24 | GPIO30INCFG | RW | GPIO30 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
23 | GPIO29INTD | RW | GPIO29 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
22:21 | GPIO29OUTCFG | RW | GPIO29 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE2 = 0x0 - FNCSEL = 0x1 - IOM3 nCE, Channel 2 M4nCE2 = 0x1 - FNCSEL = 0x1 - IOM4 nCE, Channel 2 M5nCE2 = 0x2 - FNCSEL = 0x1 - IOM5 nCE, Channel 2 M1nCE2 = 0x3 - FNCSEL = 0x1 - IOM1 nCE, Channel 2 |
20 | GPIO29INCFG | RW | GPIO29 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
19 | GPIO28INTD | RW | GPIO28 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
18:17 | GPIO28OUTCFG | RW | GPIO28 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE1 = 0x0 - FNCSEL = 0x1 - IOM3 nCE, Channel 1 M4nCE1 = 0x1 - FNCSEL = 0x1 - IOM4 nCE, Channel 1 M5nCE1 = 0x2 - FNCSEL = 0x1 - IOM5 nCE, Channel 1 MSPInCE0 = 0x3 - FNCSEL = 0x1 - MSPI nCE, Channel 0 |
16 | GPIO28INCFG | RW | GPIO28 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
15 | GPIO27INTD | RW | GPIO27 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
14:13 | GPIO27OUTCFG | RW | GPIO27 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE0 = 0x0 - FNCSEL = 0x1 - IOM3 nCE, Channel 0 M4nCE0 = 0x1 - FNCSEL = 0x1 - IOM4 nCE, Channel 0 M5nCE0 = 0x2 - FNCSEL = 0x1 - IOM5 nCE, Channel 0 M1nCE0 = 0x3 - FNCSEL = 0x1 - IOM1 nCE, Channel 0 |
12 | GPIO27INCFG | RW | GPIO27 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
11 | GPIO26INTD | RW | GPIO26 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
10:9 | GPIO26OUTCFG | RW | GPIO26 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE3 = 0x0 - FNCSEL = 0x1 - IOM3 nCE, Channel 3 M4nCE3 = 0x1 - FNCSEL = 0x1 - IOM4 nCE, Channel 3 M5nCE3 = 0x2 - FNCSEL = 0x1 - IOM5 nCE, Channel 3 M1nCE3 = 0x3 - FNCSEL = 0x1 - IOM1 nCE, Channel 3 |
8 | GPIO26INCFG | RW | GPIO26 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
7 | GPIO25INTD | RW | GPIO25 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
6:5 | GPIO25OUTCFG | RW | GPIO25 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE2 = 0x0 - FNCSEL = 0x1 - IOM3 nCE, Channel 2 M4nCE2 = 0x1 - FNCSEL = 0x1 - IOM4 nCE, Channel 2 M5nCE2 = 0x2 - FNCSEL = 0x1 - IOM5 nCE, Channel 2 M0nCE2 = 0x3 - FNCSEL = 0x1 - IOM0 nCE, Channel 2 |
4 | GPIO25INCFG | RW | GPIO25 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
3 | GPIO24INTD | RW | GPIO24 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
2:1 | GPIO24OUTCFG | RW | GPIO24 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE1 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 1 M1nCE1 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 1 M2nCE1 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 1 M5nCE1 = 0x3 - FNCSEL = 0x1 - IOM5 nCE, Channel 1 |
0 | GPIO24INCFG | RW | GPIO24 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
Instance 0 Address: | 0x40010050 |
GPIO configuration controls for GPIO[39:32]. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO39INTD
0x0 |
GPIO39OUTCFG
0x0 |
GPIO39INCFG
0x0 |
GPIO38INTD
0x0 |
GPIO38OUTCFG
0x0 |
GPIO38INCFG
0x0 |
GPIO37INTD
0x0 |
GPIO37OUTCFG
0x0 |
GPIO37INCFG
0x0 |
GPIO36INTD
0x0 |
GPIO36OUTCFG
0x0 |
GPIO36INCFG
0x0 |
GPIO35INTD
0x0 |
GPIO35OUTCFG
0x0 |
GPIO35INCFG
0x0 |
GPIO34INTD
0x0 |
GPIO34OUTCFG
0x0 |
GPIO34INCFG
0x0 |
GPIO33INTD
0x0 |
GPIO33OUTCFG
0x0 |
GPIO33INCFG
0x0 |
GPIO32INTD
0x0 |
GPIO32OUTCFG
0x0 |
GPIO32INCFG
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO39INTD | RW | GPIO39 interrupt direction. INTDIS = 0x0 - INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - INCFG = 0 - Interrupt on high to low GPIO transition |
30:29 | GPIO39OUTCFG | RW | GPIO39 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state |
28 | GPIO39INCFG | RW | GPIO39 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
27 | GPIO38INTD | RW | GPIO38 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
26:25 | GPIO38OUTCFG | RW | GPIO38 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE3 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 3 M1nCE3 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 3 M2nCE3 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 3 M5nCE3 = 0x3 - FNCSEL = 0x1 - IOM5 nCE, Channel 3 |
24 | GPIO38INCFG | RW | GPIO38 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
23 | GPIO37INTD | RW | GPIO37 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
22:21 | GPIO37OUTCFG | RW | GPIO37 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE2 = 0x0 - FNCSEL = 0x1 - IOM3 nCE, Channel 2 M4nCE2 = 0x1 - FNCSEL = 0x1 - IOM4 nCE, Channel 2 M5nCE2 = 0x2 - FNCSEL = 0x1 - IOM5 nCE, Channel 2 M0nCE2 = 0x3 - FNCSEL = 0x1 - IOM0 nCE, Channel 2 |
20 | GPIO37INCFG | RW | GPIO37 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
19 | GPIO36INTD | RW | GPIO36 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
18:17 | GPIO36OUTCFG | RW | GPIO36 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE1 = 0x0 - FNCSEL = 0x1 - IOM3 nCE, Channel 1 M4nCE1 = 0x1 - FNCSEL = 0x1 - IOM4 nCE, Channel 1 M5nCE1 = 0x2 - FNCSEL = 0x1 - IOM5 nCE, Channel 1 MSPInCE1 = 0x3 - FNCSEL = 0x1 - MSPI nCE, Channel 1 |
16 | GPIO36INCFG | RW | GPIO36 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
15 | GPIO35INTD | RW | GPIO35 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
14:13 | GPIO35OUTCFG | RW | GPIO35 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE0 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 0 M1nCE0 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 0 M2nCE0 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 0 M3nCE0 = 0x3 - FNCSEL = 0x1 - IOM3 nCE, Channel 0 |
12 | GPIO35INCFG | RW | GPIO35 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
11 | GPIO34INTD | RW | GPIO34 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
10:9 | GPIO34OUTCFG | RW | GPIO34 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE3 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 3 M1nCE3 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 3 M2nCE3 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 3 M3nCE3 = 0x3 - FNCSEL = 0x1 - IOM3 nCE, Channel 3 |
8 | GPIO34INCFG | RW | GPIO34 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
7 | GPIO33INTD | RW | GPIO33 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
6:5 | GPIO33OUTCFG | RW | GPIO33 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE2 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 2 M1nCE2 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 2 M2nCE2 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 2 M5nCE2 = 0x3 - FNCSEL = 0x1 - IOM5 nCE, Channel 2 |
4 | GPIO33INCFG | RW | GPIO33 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
3 | GPIO32INTD | RW | GPIO32 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
2:1 | GPIO32OUTCFG | RW | GPIO32 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE1 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 1 M1nCE1 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 1 M2nCE1 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 1 MSPInCE1 = 0x3 - FNCSEL = 0x1 - MSPI nCE, Channel 1 |
0 | GPIO32INCFG | RW | GPIO32 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
Instance 0 Address: | 0x40010054 |
GPIO configuration controls for GPIO[47:40]. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO47INTD
0x0 |
GPIO47OUTCFG
0x0 |
GPIO47INCFG
0x0 |
GPIO46INTD
0x0 |
GPIO46OUTCFG
0x0 |
GPIO46INCFG
0x0 |
GPIO45INTD
0x0 |
GPIO45OUTCFG
0x0 |
GPIO45INCFG
0x0 |
GPIO44INTD
0x0 |
GPIO44OUTCFG
0x0 |
GPIO44INCFG
0x0 |
GPIO43INTD
0x0 |
GPIO43OUTCFG
0x0 |
GPIO43INCFG
0x0 |
GPIO42INTD
0x0 |
GPIO42OUTCFG
0x0 |
GPIO42INCFG
0x0 |
GPIO41INTD
0x0 |
GPIO41OUTCFG
0x0 |
GPIO41INCFG
0x0 |
GPIO40INTD
0x0 |
GPIO40OUTCFG
0x0 |
GPIO40INCFG
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO47INTD | RW | GPIO47 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
30:29 | GPIO47OUTCFG | RW | GPIO47 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE1 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 1 M1nCE1 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 1 M2nCE1 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 1 M3nCE1 = 0x3 - FNCSEL = 0x1 - IOM3 nCE, Channel 1 |
28 | GPIO47INCFG | RW | GPIO47 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
27 | GPIO46INTD | RW | GPIO46 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
26:25 | GPIO46OUTCFG | RW | GPIO46 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE0 = 0x0 - FNCSEL = 0x1 - IOM3 nCE, Channel 0 M4nCE0 = 0x1 - FNCSEL = 0x1 - IOM4 nCE, Channel 0 M5nCE0 = 0x2 - FNCSEL = 0x1 - IOM5 nCE, Channel 0 MSPInCE1 = 0x3 - FNCSEL = 0x1 - MSPI nCE, Channel 1 |
24 | GPIO46INCFG | RW | GPIO46 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
23 | GPIO45INTD | RW | GPIO45 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
22:21 | GPIO45OUTCFG | RW | GPIO45 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M3nCE3 = 0x0 - FNCSEL = 0x1 - IOM3 nCE, Channel 3 M4nCE3 = 0x1 - FNCSEL = 0x1 - IOM4 nCE, Channel 3 M5nCE3 = 0x2 - FNCSEL = 0x1 - IOM5 nCE, Channel 3 M1nCE3 = 0x3 - FNCSEL = 0x1 - IOM1 nCE, Channel 3 |
20 | GPIO45INCFG | RW | GPIO45 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
19 | GPIO44INTD | RW | GPIO44 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
18:17 | GPIO44OUTCFG | RW | GPIO44 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE2 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 2 M1nCE2 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 2 M2nCE2 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 2 M5nCE2 = 0x3 - FNCSEL = 0x1 - IOM5 nCE, Channel 2 |
16 | GPIO44INCFG | RW | GPIO44 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
15 | GPIO43INTD | RW | GPIO43 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
14:13 | GPIO43OUTCFG | RW | GPIO43 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE1 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 1 M1nCE1 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 1 M2nCE1 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 1 MSPInCE1 = 0x3 - FNCSEL = 0x1 - MSPI nCE, Channel 1 |
12 | GPIO43INCFG | RW | GPIO43 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
11 | GPIO42INTD | RW | GPIO42 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
10:9 | GPIO42OUTCFG | RW | GPIO42 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE0 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 0 M1nCE0 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 0 M2nCE0 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 0 M5nCE0 = 0x3 - FNCSEL = 0x1 - IOM5 nCE, Channel 0 |
8 | GPIO42INCFG | RW | GPIO42 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
7 | GPIO41INTD | RW | GPIO41 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x0 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x0 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x0, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x0, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x0, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x0, INCFG = 0 - Interrupt on high to low GPIO transition |
6:5 | GPIO41OUTCFG | RW | GPIO41 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE1 = 0x0 - FNCSEL = 0x0 - IOM0 nCE, Channel 1 M1nCE1 = 0x1 - FNCSEL = 0x0 - IOM1 nCE, Channel 1 M2nCE1 = 0x2 - FNCSEL = 0x0 - IOM2 nCE, Channel 1 MSPInCE1 = 0x3 - FNCSEL = 0x0 - MSPI nCE, Channel 1 |
4 | GPIO41INCFG | RW | GPIO41 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
3 | GPIO40INTD | RW | GPIO40 interrupt direction. INTDIS = 0x0 - INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - INCFG = 0 - Interrupt on high to low GPIO transition |
2:1 | GPIO40OUTCFG | RW | GPIO40 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state |
0 | GPIO40INCFG | RW | GPIO40 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
Instance 0 Address: | 0x40010058 |
GPIO configuration controls for GPIO[49:48]. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
GPIO49INTD
0x0 |
GPIO49OUTCFG
0x0 |
GPIO49INCFG
0x0 |
GPIO48INTD
0x0 |
GPIO48OUTCFG
0x0 |
GPIO48INCFG
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:8 | RSVD | RO | RESERVED |
7 | GPIO49INTD | RW | GPIO49 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
6:5 | GPIO49OUTCFG | RW | GPIO49 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE3 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 3 M1nCE3 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 3 M2nCE3 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 3 M4nCE3 = 0x3 - FNCSEL = 0x1 - IOM4 nCE, Channel 3 |
4 | GPIO49INCFG | RW | GPIO49 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
3 | GPIO48INTD | RW | GPIO48 interrupt direction. nCELOW = 0x0 - FNCSEL = 0x1 - nCE polarity active low nCEHIGH = 0x1 - FNCSEL = 0x1 - nCE polarity active high INTDIS = 0x0 - FNCSEL != 0x1, INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - FNCSEL != 0x1, INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - FNCSEL != 0x1, INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - FNCSEL != 0x1, INCFG = 0 - Interrupt on high to low GPIO transition |
2:1 | GPIO48OUTCFG | RW | GPIO48 output configuration. DIS = 0x0 - FNCSEL = 0x3 - Output disabled PUSHPULL = 0x1 - FNCSEL = 0x3 - Output is push-pull OD = 0x2 - FNCSEL = 0x3 - Output is open drain TS = 0x3 - FNCSEL = 0x3 - Output is tri-state M0nCE2 = 0x0 - FNCSEL = 0x1 - IOM0 nCE, Channel 2 M1nCE2 = 0x1 - FNCSEL = 0x1 - IOM1 nCE, Channel 2 M2nCE2 = 0x2 - FNCSEL = 0x1 - IOM2 nCE, Channel 2 M3nCE2 = 0x3 - FNCSEL = 0x1 - IOM3 nCE, Channel 2 |
0 | GPIO48INCFG | RW | GPIO48 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Readback will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
Instance 0 Address: | 0x40010060 |
Key Register for all pad configuration registers
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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PADKEY
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | PADKEY | RW | Key register value. Key = 0x73 - Key |
Instance 0 Address: | 0x40010080 |
GPIO Input Register A
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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RDA
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | RDA | RO | GPIO31-0 read data. |
Instance 0 Address: | 0x40010084 |
GPIO Input Register B
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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RSVD
0x0 |
RDB
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17:0 | RDB | RO | GPIO49-32 read data. |
Instance 0 Address: | 0x40010088 |
GPIO Output Register A
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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WTA
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | WTA | RW | GPIO31-0 write data. |
Instance 0 Address: | 0x4001008C |
GPIO Output Register B
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
WTB
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17:0 | WTB | RW | GPIO49-32 write data. |
Instance 0 Address: | 0x40010090 |
GPIO Output Register A Set
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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WTSA
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | WTSA | WO | Set the GPIO31-0 write data. |
Instance 0 Address: | 0x40010094 |
GPIO Output Register B Set
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
WTSB
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17:0 | WTSB | WO | Set the GPIO49-32 write data. |
Instance 0 Address: | 0x40010098 |
GPIO Output Register A Clear
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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WTCA
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | WTCA | WO | Clear the GPIO31-0 write data. |
Instance 0 Address: | 0x4001009C |
GPIO Output Register B Clear
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
WTCB
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17:0 | WTCB | WO | Clear the GPIO49-32 write data. |
Instance 0 Address: | 0x400100A0 |
GPIO Enable Register A
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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ENA
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | ENA | RW | GPIO31-0 output enables |
Instance 0 Address: | 0x400100A4 |
GPIO Enable Register B
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
ENB
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17:0 | ENB | RW | GPIO49-32 output enables |
Instance 0 Address: | 0x400100A8 |
GPIO Enable Register A Set
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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ENSA
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | ENSA | RW | Set the GPIO31-0 output enables |
Instance 0 Address: | 0x400100AC |
GPIO Enable Register B Set
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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RSVD
0x0 |
ENSB
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17:0 | ENSB | RW | Set the GPIO49-32 output enables |
Instance 0 Address: | 0x400100B4 |
GPIO Enable Register A Clear
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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ENCA
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | ENCA | RW | Clear the GPIO31-0 output enables |
Instance 0 Address: | 0x400100B8 |
GPIO Enable Register B Clear
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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RSVD
0x0 |
ENCB
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17:0 | ENCB | RW | Clear the GPIO49-32 output enables |
Instance 0 Address: | 0x400100BC |
STIMER Capture trigger select and enable.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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RSVD
0x0 |
STPOL3
0x0 |
STSEL3
0x3f |
RSVD
0x0 |
STPOL2
0x0 |
STSEL2
0x3f |
RSVD
0x0 |
STPOL1
0x0 |
STSEL1
0x3f |
RSVD
0x0 |
STPOL0
0x0 |
STSEL0
0x3f |
Bits | Name | RW | Description |
---|---|---|---|
31 | RSVD | RO | RESERVED |
30 | STPOL3 | RW | STIMER Capture 3 Polarity. CAPLH = 0x0 - Capture on low to high GPIO transition CAPHL = 0x1 - Capture on high to low GPIO transition |
29:24 | STSEL3 | RW | STIMER Capture 3 Select. |
23 | RSVD | RO | RESERVED |
22 | STPOL2 | RW | STIMER Capture 2 Polarity. CAPLH = 0x0 - Capture on low to high GPIO transition CAPHL = 0x1 - Capture on high to low GPIO transition |
21:16 | STSEL2 | RW | STIMER Capture 2 Select. |
15 | RSVD | RO | RESERVED |
14 | STPOL1 | RW | STIMER Capture 1 Polarity. CAPLH = 0x0 - Capture on low to high GPIO transition CAPHL = 0x1 - Capture on high to low GPIO transition |
13:8 | STSEL1 | RW | STIMER Capture 1 Select. |
7 | RSVD | RO | RESERVED |
6 | STPOL0 | RW | STIMER Capture 0 Polarity. CAPLH = 0x0 - Capture on low to high GPIO transition CAPHL = 0x1 - Capture on high to low GPIO transition |
5:0 | STSEL0 | RW | STIMER Capture 0 Select. |
Instance 0 Address: | 0x400100C0 |
IOMSTR0 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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RSVD
0x0 |
IOM0IRQ
0x3f |
Bits | Name | RW | Description |
---|---|---|---|
31:6 | RSVD | RO | RESERVED |
5:0 | IOM0IRQ | RW | IOMSTR0 IRQ pad select. |
Instance 0 Address: | 0x400100C4 |
IOMSTR1 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
IOM1IRQ
0x3f |
Bits | Name | RW | Description |
---|---|---|---|
31:6 | RSVD | RO | RESERVED |
5:0 | IOM1IRQ | RW | IOMSTR1 IRQ pad select. |
Instance 0 Address: | 0x400100C8 |
IOMSTR2 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
IOM2IRQ
0x3f |
Bits | Name | RW | Description |
---|---|---|---|
31:6 | RSVD | RO | RESERVED |
5:0 | IOM2IRQ | RW | IOMSTR2 IRQ pad select. |
Instance 0 Address: | 0x400100CC |
IOMSTR3 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
IOM3IRQ
0x3f |
Bits | Name | RW | Description |
---|---|---|---|
31:6 | RSVD | RO | RESERVED |
5:0 | IOM3IRQ | RW | IOMSTR3 IRQ pad select. |
Instance 0 Address: | 0x400100D0 |
IOMSTR4 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
IOM4IRQ
0x3f |
Bits | Name | RW | Description |
---|---|---|---|
31:6 | RSVD | RO | RESERVED |
5:0 | IOM4IRQ | RW | IOMSTR4 IRQ pad select. |
Instance 0 Address: | 0x400100D4 |
IOMSTR5 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
IOM5IRQ
0x3f |
Bits | Name | RW | Description |
---|---|---|---|
31:6 | RSVD | RO | RESERVED |
5:0 | IOM5IRQ | RW | IOMSTR5 IRQ pad select. |
Instance 0 Address: | 0x400100D8 |
BLE IF IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
BLEIFIRQ
0x3f |
Bits | Name | RW | Description |
---|---|---|---|
31:6 | RSVD | RO | RESERVED |
5:0 | BLEIFIRQ | RW | BLEIF IRQ pad select. |
Instance 0 Address: | 0x400100DC |
GPIO Observation mode sample register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
OBS_DATA
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:16 | RSVD | RO | RESERVED |
15:0 | OBS_DATA | RW | Sample of the data output on the GPIO observation port. May have async sampling issues, as the data is not synronized to the read operation. Intended for debug purposes only |
Instance 0 Address: | 0x400100E0 |
This register has additional configuration control for pads 3, 2, 1, 0
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD3_SR
0x0 |
RSVD
0x0 |
PAD3_DS1
0x0 |
RSVD
0x0 |
PAD2_SR
0x0 |
RSVD
0x0 |
PAD2_DS1
0x0 |
RSVD
0x0 |
PAD1_SR
0x0 |
RSVD
0x0 |
PAD1_DS1
0x0 |
RSVD
0x0 |
PAD0_SR
0x0 |
RSVD
0x0 |
PAD0_DS1
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28 | PAD3_SR | RW | Pad 3 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
27:25 | RSVD | RO | RESERVED |
24 | PAD3_DS1 | RW | Pad 3 high order drive strength selection. Used in conjunction with PAD3STRNG field to set the pad drive strength. |
23:21 | RSVD | RO | RESERVED |
20 | PAD2_SR | RW | Pad 2 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
19:17 | RSVD | RO | RESERVED |
16 | PAD2_DS1 | RW | Pad 2 high order drive strength selection. Used in conjunction with PAD2STRNG field to set the pad drive strength. |
15:13 | RSVD | RO | RESERVED |
12 | PAD1_SR | RW | Pad 1 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
11:9 | RSVD | RO | RESERVED |
8 | PAD1_DS1 | RW | Pad 1 high order drive strength selection. Used in conjunction with PAD1STRNG field to set the pad drive strength. |
7:5 | RSVD | RO | RESERVED |
4 | PAD0_SR | RW | Pad 0 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
3:1 | RSVD | RO | RESERVED |
0 | PAD0_DS1 | RW | Pad 0 high order drive strength selection. Used in conjunction with PAD0STRNG field to set the pad drive strength. |
Instance 0 Address: | 0x400100E4 |
This register has additional configuration control for pads 7, 6, 5, 4
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD7_SR
0x0 |
RSVD
0x0 |
PAD7_DS1
0x0 |
RSVD
0x0 |
PAD6_SR
0x0 |
RSVD
0x0 |
PAD6_DS1
0x0 |
RSVD
0x0 |
PAD5_SR
0x0 |
RSVD
0x0 |
PAD5_DS1
0x0 |
RSVD
0x0 |
PAD4_SR
0x0 |
RSVD
0x0 |
PAD4_DS1
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28 | PAD7_SR | RW | Pad 7 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
27:25 | RSVD | RO | RESERVED |
24 | PAD7_DS1 | RW | Pad 7 high order drive strength selection. Used in conjunction with PAD7STRNG field to set the pad drive strength. |
23:21 | RSVD | RO | RESERVED |
20 | PAD6_SR | RW | Pad 6 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
19:17 | RSVD | RO | RESERVED |
16 | PAD6_DS1 | RW | Pad 6 high order drive strength selection. Used in conjunction with PAD6STRNG field to set the pad drive strength. |
15:13 | RSVD | RO | RESERVED |
12 | PAD5_SR | RW | Pad 5 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
11:9 | RSVD | RO | RESERVED |
8 | PAD5_DS1 | RW | Pad 5 high order drive strength selection. Used in conjunction with PAD5STRNG field to set the pad drive strength. |
7:5 | RSVD | RO | RESERVED |
4 | PAD4_SR | RW | Pad 4 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
3:1 | RSVD | RO | RESERVED |
0 | PAD4_DS1 | RW | Pad 4 high order drive strength selection. Used in conjunction with PAD4STRNG field to set the pad drive strength. |
Instance 0 Address: | 0x400100E8 |
This register has additional configuration control for pads 11, 10, 9, 8
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD11_SR
0x0 |
RSVD
0x0 |
PAD11_DS1
0x0 |
RSVD
0x0 |
PAD10_SR
0x0 |
RSVD
0x0 |
PAD10_DS1
0x0 |
RSVD
0x0 |
PAD9_SR
0x0 |
RSVD
0x0 |
PAD9_DS1
0x0 |
RSVD
0x0 |
PAD8_SR
0x0 |
RSVD
0x0 |
PAD8_DS1
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28 | PAD11_SR | RW | Pad 11 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
27:25 | RSVD | RO | RESERVED |
24 | PAD11_DS1 | RW | Pad 11 high order drive strength selection. Used in conjunction with PAD11STRNG field to set the pad drive strength. |
23:21 | RSVD | RO | RESERVED |
20 | PAD10_SR | RW | Pad 10 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
19:17 | RSVD | RO | RESERVED |
16 | PAD10_DS1 | RW | Pad 10 high order drive strength selection. Used in conjunction with PAD10STRNG field to set the pad drive strength. |
15:13 | RSVD | RO | RESERVED |
12 | PAD9_SR | RW | Pad 9 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
11:9 | RSVD | RO | RESERVED |
8 | PAD9_DS1 | RW | Pad 9 high order drive strength selection. Used in conjunction with PAD9STRNG field to set the pad drive strength. |
7:5 | RSVD | RO | RESERVED |
4 | PAD8_SR | RW | Pad 8 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
3:1 | RSVD | RO | RESERVED |
0 | PAD8_DS1 | RW | Pad 8 high order drive strength selection. Used in conjunction with PAD8STRNG field to set the pad drive strength. |
Instance 0 Address: | 0x400100EC |
This register has additional configuration control for pads 15, 14, 13, 12
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD15_SR
0x0 |
RSVD
0x0 |
PAD15_DS1
0x0 |
RSVD
0x0 |
PAD14_SR
0x0 |
RSVD
0x0 |
PAD14_DS1
0x0 |
RSVD
0x0 |
PAD13_SR
0x0 |
RSVD
0x0 |
PAD13_DS1
0x0 |
RSVD
0x0 |
PAD12_SR
0x0 |
RSVD
0x0 |
PAD12_DS1
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28 | PAD15_SR | RW | Pad 15 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
27:25 | RSVD | RO | RESERVED |
24 | PAD15_DS1 | RW | Pad 15 high order drive strength selection. Used in conjunction with PAD15STRNG field to set the pad drive strength. |
23:21 | RSVD | RO | RESERVED |
20 | PAD14_SR | RW | Pad 14 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
19:17 | RSVD | RO | RESERVED |
16 | PAD14_DS1 | RW | Pad 14 high order drive strength selection. Used in conjunction with PAD14STRNG field to set the pad drive strength. |
15:13 | RSVD | RO | RESERVED |
12 | PAD13_SR | RW | Pad 13 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
11:9 | RSVD | RO | RESERVED |
8 | PAD13_DS1 | RW | Pad 13 high order drive strength selection. Used in conjunction with PAD13STRNG field to set the pad drive strength. |
7:5 | RSVD | RO | RESERVED |
4 | PAD12_SR | RW | Pad 12 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
3:1 | RSVD | RO | RESERVED |
0 | PAD12_DS1 | RW | Pad 12 high order drive strength selection. Used in conjunction with PAD12STRNG field to set the pad drive strength. |
Instance 0 Address: | 0x400100F0 |
This register has additional configuration control for pads 19, 18, 17, 16
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD19_SR
0x0 |
RSVD
0x0 |
PAD19_DS1
0x0 |
RSVD
0x0 |
PAD18_SR
0x0 |
RSVD
0x0 |
PAD18_DS1
0x0 |
RSVD
0x0 |
PAD17_SR
0x0 |
RSVD
0x0 |
PAD17_DS1
0x0 |
RSVD
0x0 |
PAD16_SR
0x0 |
RSVD
0x0 |
PAD16_DS1
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28 | PAD19_SR | RW | Pad 19 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
27:25 | RSVD | RO | RESERVED |
24 | PAD19_DS1 | RW | Pad 19 high order drive strength selection. Used in conjunction with PAD19STRNG field to set the pad drive strength. |
23:21 | RSVD | RO | RESERVED |
20 | PAD18_SR | RW | Pad 18 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
19:17 | RSVD | RO | RESERVED |
16 | PAD18_DS1 | RW | Pad 18 high order drive strength selection. Used in conjunction with PAD18STRNG field to set the pad drive strength. |
15:13 | RSVD | RO | RESERVED |
12 | PAD17_SR | RW | Pad 17 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
11:9 | RSVD | RO | RESERVED |
8 | PAD17_DS1 | RW | Pad 17 high order drive strength selection. Used in conjunction with PAD17STRNG field to set the pad drive strength. |
7:5 | RSVD | RO | RESERVED |
4 | PAD16_SR | RW | Pad 16 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
3:1 | RSVD | RO | RESERVED |
0 | PAD16_DS1 | RW | Pad 16 high order drive strength selection. Used in conjunction with PAD16STRNG field to set the pad drive strength. |
Instance 0 Address: | 0x400100F4 |
This register has additional configuration control for pads 23, 22, 21, 20
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD23_SR
0x0 |
RSVD
0x0 |
PAD23_DS1
0x0 |
RSVD
0x0 |
PAD22_SR
0x0 |
RSVD
0x0 |
PAD22_DS1
0x0 |
RSVD
0x0 |
PAD21_SR
0x0 |
RSVD
0x0 |
PAD21_DS1
0x0 |
RSVD
0x0 |
PAD20_SR
0x0 |
RSVD
0x0 |
PAD20_DS1
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28 | PAD23_SR | RW | Pad 23 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
27:25 | RSVD | RO | RESERVED |
24 | PAD23_DS1 | RW | Pad 23 high order drive strength selection. Used in conjunction with PAD23STRNG field to set the pad drive strength. |
23:21 | RSVD | RO | RESERVED |
20 | PAD22_SR | RW | Pad 22 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
19:17 | RSVD | RO | RESERVED |
16 | PAD22_DS1 | RW | Pad 22 high order drive strength selection. Used in conjunction with PAD22STRNG field to set the pad drive strength. |
15:13 | RSVD | RO | RESERVED |
12 | PAD21_SR | RW | Pad 21 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
11:9 | RSVD | RO | RESERVED |
8 | PAD21_DS1 | RW | Pad 21 high order drive strength selection. Used in conjunction with PAD21STRNG field to set the pad drive strength. |
7:5 | RSVD | RO | RESERVED |
4 | PAD20_SR | RW | Pad 20 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
3:1 | RSVD | RO | RESERVED |
0 | PAD20_DS1 | RW | Pad 20 high order drive strength selection. Used in conjunction with PAD20STRNG field to set the pad drive strength. |
Instance 0 Address: | 0x400100F8 |
This register has additional configuration control for pads 27, 26, 25, 24
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD27_SR
0x0 |
RSVD
0x0 |
PAD27_DS1
0x0 |
RSVD
0x0 |
PAD26_SR
0x0 |
RSVD
0x0 |
PAD26_DS1
0x0 |
RSVD
0x0 |
PAD25_SR
0x0 |
RSVD
0x0 |
PAD25_DS1
0x0 |
RSVD
0x0 |
PAD24_SR
0x0 |
RSVD
0x0 |
PAD24_DS1
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28 | PAD27_SR | RW | Pad 27 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
27:25 | RSVD | RO | RESERVED |
24 | PAD27_DS1 | RW | Pad 27 high order drive strength selection. Used in conjunction with PAD27STRNG field to set the pad drive strength. |
23:21 | RSVD | RO | RESERVED |
20 | PAD26_SR | RW | Pad 26 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
19:17 | RSVD | RO | RESERVED |
16 | PAD26_DS1 | RW | Pad 26 high order drive strength selection. Used in conjunction with PAD26STRNG field to set the pad drive strength. |
15:13 | RSVD | RO | RESERVED |
12 | PAD25_SR | RW | Pad 25 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
11:9 | RSVD | RO | RESERVED |
8 | PAD25_DS1 | RW | Pad 25 high order drive strength selection. Used in conjunction with PAD25STRNG field to set the pad drive strength. |
7:5 | RSVD | RO | RESERVED |
4 | PAD24_SR | RW | Pad 24 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
3:1 | RSVD | RO | RESERVED |
0 | PAD24_DS1 | RW | Pad 24 high order drive strength selection. Used in conjunction with PAD24STRNG field to set the pad drive strength. |
Instance 0 Address: | 0x400100FC |
This register has additional configuration control for pads 31, 30, 29, 28
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD31_SR
0x0 |
RSVD
0x0 |
PAD31_DS1
0x0 |
RSVD
0x0 |
PAD30_SR
0x0 |
RSVD
0x0 |
PAD30_DS1
0x0 |
RSVD
0x0 |
PAD29_SR
0x0 |
RSVD
0x0 |
PAD29_DS1
0x0 |
RSVD
0x0 |
PAD28_SR
0x0 |
RSVD
0x0 |
PAD28_DS1
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28 | PAD31_SR | RW | Pad 31 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
27:25 | RSVD | RO | RESERVED |
24 | PAD31_DS1 | RW | Pad 31 high order drive strength selection. Used in conjunction with PAD31STRNG field to set the pad drive strength. |
23:21 | RSVD | RO | RESERVED |
20 | PAD30_SR | RW | Pad 30 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
19:17 | RSVD | RO | RESERVED |
16 | PAD30_DS1 | RW | Pad 30 high order drive strength selection. Used in conjunction with PAD30STRNG field to set the pad drive strength. |
15:13 | RSVD | RO | RESERVED |
12 | PAD29_SR | RW | Pad 29 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
11:9 | RSVD | RO | RESERVED |
8 | PAD29_DS1 | RW | Pad 29 high order drive strength selection. Used in conjunction with PAD29STRNG field to set the pad drive strength. |
7:5 | RSVD | RO | RESERVED |
4 | PAD28_SR | RW | Pad 28 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
3:1 | RSVD | RO | RESERVED |
0 | PAD28_DS1 | RW | Pad 28 high order drive strength selection. Used in conjunction with PAD28STRNG field to set the pad drive strength. |
Instance 0 Address: | 0x40010100 |
This register has additional configuration control for pads 35, 34, 33, 32
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD35_SR
0x0 |
RSVD
0x0 |
PAD35_DS1
0x0 |
RSVD
0x0 |
PAD34_SR
0x0 |
RSVD
0x0 |
PAD34_DS1
0x0 |
RSVD
0x0 |
PAD33_SR
0x0 |
RSVD
0x0 |
PAD33_DS1
0x0 |
RSVD
0x0 |
PAD32_SR
0x0 |
RSVD
0x0 |
PAD32_DS1
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28 | PAD35_SR | RW | Pad 35 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
27:25 | RSVD | RO | RESERVED |
24 | PAD35_DS1 | RW | Pad 35 high order drive strength selection. Used in conjunction with PAD35STRNG field to set the pad drive strength. |
23:21 | RSVD | RO | RESERVED |
20 | PAD34_SR | RW | Pad 34 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
19:17 | RSVD | RO | RESERVED |
16 | PAD34_DS1 | RW | Pad 34 high order drive strength selection. Used in conjunction with PAD34STRNG field to set the pad drive strength. |
15:13 | RSVD | RO | RESERVED |
12 | PAD33_SR | RW | Pad 33 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
11:9 | RSVD | RO | RESERVED |
8 | PAD33_DS1 | RW | Pad 33 high order drive strength selection. Used in conjunction with PAD33STRNG field to set the pad drive strength. |
7:5 | RSVD | RO | RESERVED |
4 | PAD32_SR | RW | Pad 32 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
3:1 | RSVD | RO | RESERVED |
0 | PAD32_DS1 | RW | Pad 32 high order drive strength selection. Used in conjunction with PAD32STRNG field to set the pad drive strength. |
Instance 0 Address: | 0x40010104 |
This register has additional configuration control for pads 39, 38, 37, 36
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD39_SR
0x0 |
RSVD
0x0 |
PAD39_DS1
0x0 |
RSVD
0x0 |
PAD38_SR
0x0 |
RSVD
0x0 |
PAD38_DS1
0x0 |
RSVD
0x0 |
PAD37_SR
0x0 |
RSVD
0x0 |
PAD37_DS1
0x0 |
RSVD
0x0 |
PAD36_SR
0x0 |
RSVD
0x0 |
PAD36_DS1
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28 | PAD39_SR | RW | Pad 39 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
27:25 | RSVD | RO | RESERVED |
24 | PAD39_DS1 | RW | Pad 39 high order drive strength selection. Used in conjunction with PAD39STRNG field to set the pad drive strength. |
23:21 | RSVD | RO | RESERVED |
20 | PAD38_SR | RW | Pad 38 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
19:17 | RSVD | RO | RESERVED |
16 | PAD38_DS1 | RW | Pad 38 high order drive strength selection. Used in conjunction with PAD38STRNG field to set the pad drive strength. |
15:13 | RSVD | RO | RESERVED |
12 | PAD37_SR | RW | Pad 37 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
11:9 | RSVD | RO | RESERVED |
8 | PAD37_DS1 | RW | Pad 37 high order drive strength selection. Used in conjunction with PAD37STRNG field to set the pad drive strength. |
7:5 | RSVD | RO | RESERVED |
4 | PAD36_SR | RW | Pad 36 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
3:1 | RSVD | RO | RESERVED |
0 | PAD36_DS1 | RW | Pad 36 high order drive strength selection. Used in conjunction with PAD36STRNG field to set the pad drive strength. |
Instance 0 Address: | 0x40010108 |
This register has additional configuration control for pads 43, 42, 41, 40
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD43_SR
0x0 |
RSVD
0x0 |
PAD43_DS1
0x0 |
RSVD
0x0 |
PAD42_SR
0x0 |
RSVD
0x0 |
PAD42_DS1
0x0 |
RSVD
0x0 |
PAD41_SR
0x0 |
RSVD
0x0 |
PAD41_DS1
0x0 |
RSVD
0x0 |
PAD40_SR
0x0 |
RSVD
0x0 |
PAD40_DS1
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28 | PAD43_SR | RW | Pad 43 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
27:25 | RSVD | RO | RESERVED |
24 | PAD43_DS1 | RW | Pad 43 high order drive strength selection. Used in conjunction with PAD43STRNG field to set the pad drive strength. |
23:21 | RSVD | RO | RESERVED |
20 | PAD42_SR | RW | Pad 42 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
19:17 | RSVD | RO | RESERVED |
16 | PAD42_DS1 | RW | Pad 42 high order drive strength selection. Used in conjunction with PAD42STRNG field to set the pad drive strength. |
15:13 | RSVD | RO | RESERVED |
12 | PAD41_SR | RW | Pad 41 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
11:9 | RSVD | RO | RESERVED |
8 | PAD41_DS1 | RW | Pad 41 high order drive strength selection. Used in conjunction with PAD41STRNG field to set the pad drive strength. |
7:5 | RSVD | RO | RESERVED |
4 | PAD40_SR | RW | Pad 40 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
3:1 | RSVD | RO | RESERVED |
0 | PAD40_DS1 | RW | Pad 40 high order drive strength selection. Used in conjunction with PAD40STRNG field to set the pad drive strength. |
Instance 0 Address: | 0x4001010C |
This register has additional configuration control for pads 47, 46, 45, 44
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD47_SR
0x0 |
RSVD
0x0 |
PAD47_DS1
0x0 |
RSVD
0x0 |
PAD46_SR
0x0 |
RSVD
0x0 |
PAD46_DS1
0x0 |
RSVD
0x0 |
PAD45_SR
0x0 |
RSVD
0x0 |
PAD45_DS1
0x0 |
RSVD
0x0 |
PAD44_SR
0x0 |
RSVD
0x0 |
PAD44_DS1
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28 | PAD47_SR | RW | Pad 47 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
27:25 | RSVD | RO | RESERVED |
24 | PAD47_DS1 | RW | Pad 47 high order drive strength selection. Used in conjunction with PAD47STRNG field to set the pad drive strength. |
23:21 | RSVD | RO | RESERVED |
20 | PAD46_SR | RW | Pad 46 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
19:17 | RSVD | RO | RESERVED |
16 | PAD46_DS1 | RW | Pad 46 high order drive strength selection. Used in conjunction with PAD46STRNG field to set the pad drive strength. |
15:13 | RSVD | RO | RESERVED |
12 | PAD45_SR | RW | Pad 45 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
11:9 | RSVD | RO | RESERVED |
8 | PAD45_DS1 | RW | Pad 45 high order drive strength selection. Used in conjunction with PAD45STRNG field to set the pad drive strength. |
7:5 | RSVD | RO | RESERVED |
4 | PAD44_SR | RW | Pad 44 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
3:1 | RSVD | RO | RESERVED |
0 | PAD44_DS1 | RW | Pad 44 high order drive strength selection. Used in conjunction with PAD44STRNG field to set the pad drive strength. |
Instance 0 Address: | 0x40010110 |
This register has additional configuration control for pads 49, 48
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD49_SR
0x0 |
RSVD
0x0 |
PAD49_DS1
0x0 |
RSVD
0x0 |
PAD48_SR
0x0 |
RSVD
0x0 |
PAD48_DS1
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:13 | RSVD | RO | RESERVED |
12 | PAD49_SR | RW | Pad 49 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
11:9 | RSVD | RO | RESERVED |
8 | PAD49_DS1 | RW | Pad 49 high order drive strength selection. Used in conjunction with PAD49STRNG field to set the pad drive strength. |
7:5 | RSVD | RO | RESERVED |
4 | PAD48_SR | RW | Pad 48 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
3:1 | RSVD | RO | RESERVED |
0 | PAD48_DS1 | RW | Pad 48 high order drive strength selection. Used in conjunction with PAD48STRNG field to set the pad drive strength. |
Instance 0 Address: | 0x40010114 |
Scard card detect select.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
SCDET
0x3f |
Bits | Name | RW | Description |
---|---|---|---|
31:6 | RSVD | RO | RESERVED |
5:0 | SCDET | RW | SCARD card detect pad select. |
Instance 0 Address: | 0x40010118 |
Pad enable configuration.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EN31
0x1 |
EN30
0x1 |
EN29
0x1 |
EN28
0x1 |
EN27
0x1 |
EN26
0x1 |
EN25
0x1 |
EN24
0x1 |
EN23
0x1 |
EN22
0x1 |
EN21
0x1 |
EN20
0x1 |
EN19
0x1 |
EN18
0x1 |
EN17
0x1 |
EN16
0x1 |
EN15
0x1 |
EN14
0x1 |
EN13
0x1 |
EN12
0x1 |
EN11
0x1 |
EN10
0x1 |
EN9
0x1 |
EN8
0x1 |
EN7
0x1 |
EN6
0x1 |
EN5
0x1 |
EN4
0x1 |
EN3
0x1 |
EN2
0x1 |
EN1
0x1 |
EN0
0x1 |
Bits | Name | RW | Description |
---|---|---|---|
31 | EN31 | RW | CT31 Enable DIS = 0x1 - Disable CT31 for output EN = 0x0 - Enable CT31 for output |
30 | EN30 | RW | CT30 Enable DIS = 0x1 - Disable CT30 for output EN = 0x0 - Enable CT30 for output |
29 | EN29 | RW | CT29 Enable DIS = 0x1 - Disable CT29 for output EN = 0x0 - Enable CT29 for output |
28 | EN28 | RW | CT28 Enable DIS = 0x1 - Disable CT28 for output EN = 0x0 - Enable CT28 for output |
27 | EN27 | RW | CT27 Enable DIS = 0x1 - Disable CT27 for output EN = 0x0 - Enable CT27 for output |
26 | EN26 | RW | CT26 Enable DIS = 0x1 - Disable CT26 for output EN = 0x0 - Enable CT26 for output |
25 | EN25 | RW | CT25 Enable DIS = 0x1 - Disable CT25 for output EN = 0x0 - Enable CT25 for output |
24 | EN24 | RW | CT24 Enable DIS = 0x1 - Disable CT24 for output EN = 0x0 - Enable CT24 for output |
23 | EN23 | RW | CT23 Enable DIS = 0x1 - Disable CT23 for output EN = 0x0 - Enable CT23 for output |
22 | EN22 | RW | CT22 Enable DIS = 0x1 - Disable CT22 for output EN = 0x0 - Enable CT22 for output |
21 | EN21 | RW | CT21 Enable DIS = 0x1 - Disable CT21 for output EN = 0x0 - Enable CT21 for output |
20 | EN20 | RW | CT20 Enable DIS = 0x1 - Disable CT20 for output EN = 0x0 - Enable CT20 for output |
19 | EN19 | RW | CT19 Enable DIS = 0x1 - Disable CT19 for output EN = 0x0 - Enable CT19 for output |
18 | EN18 | RW | CT18 Enable DIS = 0x1 - Disable CT18 for output EN = 0x0 - Enable CT18 for output |
17 | EN17 | RW | CT17 Enable DIS = 0x1 - Disable CT17 for output EN = 0x0 - Enable CT17 for output |
16 | EN16 | RW | CT16 Enable DIS = 0x1 - Disable CT16 for output EN = 0x0 - Enable CT16 for output |
15 | EN15 | RW | CT15 Enable DIS = 0x1 - Disable CT15 for output EN = 0x0 - Enable CT15 for output |
14 | EN14 | RW | CT14 Enable DIS = 0x1 - Disable CT14 for output EN = 0x0 - Enable CT14 for output |
13 | EN13 | RW | CT13 Enable DIS = 0x1 - Disable CT13 for output EN = 0x0 - Enable CT13 for output |
12 | EN12 | RW | CT12 Enable DIS = 0x1 - Disable CT12 for output EN = 0x0 - Enable CT12 for output |
11 | EN11 | RW | CT11 Enable DIS = 0x1 - Disable CT11 for output EN = 0x0 - Enable CT11 for output |
10 | EN10 | RW | CT10 Enable DIS = 0x1 - Disable CT10 for output EN = 0x0 - Enable CT10 for output |
9 | EN9 | RW | CT9 Enable DIS = 0x0 - Disable CT9 for output EN = 0x0 - Enable CT9 for output |
8 | EN8 | RW | CT8 Enable DIS = 0x1 - Disable CT8 for output EN = 0x0 - Enable CT8 for output |
7 | EN7 | RW | CT7 Enable DIS = 0x1 - Disable CT7 for output EN = 0x0 - Enable CT7 for output |
6 | EN6 | RW | CT6 Enable DIS = 0x1 - Disable CT6 for output EN = 0x0 - Enable CT6 for output |
5 | EN5 | RW | CT5 Enable DIS = 0x1 - Disable CT5 for output EN = 0x0 - Enable CT5 for output |
4 | EN4 | RW | CT4 Enable DIS = 0x1 - Disable CT4 for output EN = 0x0 - Enable CT4 for output |
3 | EN3 | RW | CT3 Enable DIS = 0x1 - Disable CT3 for output EN = 0x0 - Enable CT3 for output |
2 | EN2 | RW | CT2 Enable DIS = 0x1 - Disable CT2 for output EN = 0x0 - Enable CT2 for output |
1 | EN1 | RW | CT1 Enable DIS = 0x1 - Disable CT1 for output EN = 0x0 - Enable CT1 for output |
0 | EN0 | RW | CT0 Enable DIS = 0x1 - Disable CT0 for output EN = 0x0 - Enable CT0 for output |
Instance 0 Address: | 0x40010200 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO31
0x0 |
GPIO30
0x0 |
GPIO29
0x0 |
GPIO28
0x0 |
GPIO27
0x0 |
GPIO26
0x0 |
GPIO25
0x0 |
GPIO24
0x0 |
GPIO23
0x0 |
GPIO22
0x0 |
GPIO21
0x0 |
GPIO20
0x0 |
GPIO19
0x0 |
GPIO18
0x0 |
GPIO17
0x0 |
GPIO16
0x0 |
GPIO15
0x0 |
GPIO14
0x0 |
GPIO13
0x0 |
GPIO12
0x0 |
GPIO11
0x0 |
GPIO10
0x0 |
GPIO9
0x0 |
GPIO8
0x0 |
GPIO7
0x0 |
GPIO6
0x0 |
GPIO5
0x0 |
GPIO4
0x0 |
GPIO3
0x0 |
GPIO2
0x0 |
GPIO1
0x0 |
GPIO0
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO31 | RW | GPIO31 interrupt. |
30 | GPIO30 | RW | GPIO30 interrupt. |
29 | GPIO29 | RW | GPIO29 interrupt. |
28 | GPIO28 | RW | GPIO28 interrupt. |
27 | GPIO27 | RW | GPIO27 interrupt. |
26 | GPIO26 | RW | GPIO26 interrupt. |
25 | GPIO25 | RW | GPIO25 interrupt. |
24 | GPIO24 | RW | GPIO24 interrupt. |
23 | GPIO23 | RW | GPIO23 interrupt. |
22 | GPIO22 | RW | GPIO22 interrupt. |
21 | GPIO21 | RW | GPIO21 interrupt. |
20 | GPIO20 | RW | GPIO20 interrupt. |
19 | GPIO19 | RW | GPIO19 interrupt. |
18 | GPIO18 | RW | GPIO18interrupt. |
17 | GPIO17 | RW | GPIO17 interrupt. |
16 | GPIO16 | RW | GPIO16 interrupt. |
15 | GPIO15 | RW | GPIO15 interrupt. |
14 | GPIO14 | RW | GPIO14 interrupt. |
13 | GPIO13 | RW | GPIO13 interrupt. |
12 | GPIO12 | RW | GPIO12 interrupt. |
11 | GPIO11 | RW | GPIO11 interrupt. |
10 | GPIO10 | RW | GPIO10 interrupt. |
9 | GPIO9 | RW | GPIO9 interrupt. |
8 | GPIO8 | RW | GPIO8 interrupt. |
7 | GPIO7 | RW | GPIO7 interrupt. |
6 | GPIO6 | RW | GPIO6 interrupt. |
5 | GPIO5 | RW | GPIO5 interrupt. |
4 | GPIO4 | RW | GPIO4 interrupt. |
3 | GPIO3 | RW | GPIO3 interrupt. |
2 | GPIO2 | RW | GPIO2 interrupt. |
1 | GPIO1 | RW | GPIO1 interrupt. |
0 | GPIO0 | RW | GPIO0 interrupt. |
Instance 0 Address: | 0x40010204 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO31
0x0 |
GPIO30
0x0 |
GPIO29
0x0 |
GPIO28
0x0 |
GPIO27
0x0 |
GPIO26
0x0 |
GPIO25
0x0 |
GPIO24
0x0 |
GPIO23
0x0 |
GPIO22
0x0 |
GPIO21
0x0 |
GPIO20
0x0 |
GPIO19
0x0 |
GPIO18
0x0 |
GPIO17
0x0 |
GPIO16
0x0 |
GPIO15
0x0 |
GPIO14
0x0 |
GPIO13
0x0 |
GPIO12
0x0 |
GPIO11
0x0 |
GPIO10
0x0 |
GPIO9
0x0 |
GPIO8
0x0 |
GPIO7
0x0 |
GPIO6
0x0 |
GPIO5
0x0 |
GPIO4
0x0 |
GPIO3
0x0 |
GPIO2
0x0 |
GPIO1
0x0 |
GPIO0
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO31 | RW | GPIO31 interrupt. |
30 | GPIO30 | RW | GPIO30 interrupt. |
29 | GPIO29 | RW | GPIO29 interrupt. |
28 | GPIO28 | RW | GPIO28 interrupt. |
27 | GPIO27 | RW | GPIO27 interrupt. |
26 | GPIO26 | RW | GPIO26 interrupt. |
25 | GPIO25 | RW | GPIO25 interrupt. |
24 | GPIO24 | RW | GPIO24 interrupt. |
23 | GPIO23 | RW | GPIO23 interrupt. |
22 | GPIO22 | RW | GPIO22 interrupt. |
21 | GPIO21 | RW | GPIO21 interrupt. |
20 | GPIO20 | RW | GPIO20 interrupt. |
19 | GPIO19 | RW | GPIO19 interrupt. |
18 | GPIO18 | RW | GPIO18interrupt. |
17 | GPIO17 | RW | GPIO17 interrupt. |
16 | GPIO16 | RW | GPIO16 interrupt. |
15 | GPIO15 | RW | GPIO15 interrupt. |
14 | GPIO14 | RW | GPIO14 interrupt. |
13 | GPIO13 | RW | GPIO13 interrupt. |
12 | GPIO12 | RW | GPIO12 interrupt. |
11 | GPIO11 | RW | GPIO11 interrupt. |
10 | GPIO10 | RW | GPIO10 interrupt. |
9 | GPIO9 | RW | GPIO9 interrupt. |
8 | GPIO8 | RW | GPIO8 interrupt. |
7 | GPIO7 | RW | GPIO7 interrupt. |
6 | GPIO6 | RW | GPIO6 interrupt. |
5 | GPIO5 | RW | GPIO5 interrupt. |
4 | GPIO4 | RW | GPIO4 interrupt. |
3 | GPIO3 | RW | GPIO3 interrupt. |
2 | GPIO2 | RW | GPIO2 interrupt. |
1 | GPIO1 | RW | GPIO1 interrupt. |
0 | GPIO0 | RW | GPIO0 interrupt. |
Instance 0 Address: | 0x40010208 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO31
0x0 |
GPIO30
0x0 |
GPIO29
0x0 |
GPIO28
0x0 |
GPIO27
0x0 |
GPIO26
0x0 |
GPIO25
0x0 |
GPIO24
0x0 |
GPIO23
0x0 |
GPIO22
0x0 |
GPIO21
0x0 |
GPIO20
0x0 |
GPIO19
0x0 |
GPIO18
0x0 |
GPIO17
0x0 |
GPIO16
0x0 |
GPIO15
0x0 |
GPIO14
0x0 |
GPIO13
0x0 |
GPIO12
0x0 |
GPIO11
0x0 |
GPIO10
0x0 |
GPIO9
0x0 |
GPIO8
0x0 |
GPIO7
0x0 |
GPIO6
0x0 |
GPIO5
0x0 |
GPIO4
0x0 |
GPIO3
0x0 |
GPIO2
0x0 |
GPIO1
0x0 |
GPIO0
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO31 | RW | GPIO31 interrupt. |
30 | GPIO30 | RW | GPIO30 interrupt. |
29 | GPIO29 | RW | GPIO29 interrupt. |
28 | GPIO28 | RW | GPIO28 interrupt. |
27 | GPIO27 | RW | GPIO27 interrupt. |
26 | GPIO26 | RW | GPIO26 interrupt. |
25 | GPIO25 | RW | GPIO25 interrupt. |
24 | GPIO24 | RW | GPIO24 interrupt. |
23 | GPIO23 | RW | GPIO23 interrupt. |
22 | GPIO22 | RW | GPIO22 interrupt. |
21 | GPIO21 | RW | GPIO21 interrupt. |
20 | GPIO20 | RW | GPIO20 interrupt. |
19 | GPIO19 | RW | GPIO19 interrupt. |
18 | GPIO18 | RW | GPIO18interrupt. |
17 | GPIO17 | RW | GPIO17 interrupt. |
16 | GPIO16 | RW | GPIO16 interrupt. |
15 | GPIO15 | RW | GPIO15 interrupt. |
14 | GPIO14 | RW | GPIO14 interrupt. |
13 | GPIO13 | RW | GPIO13 interrupt. |
12 | GPIO12 | RW | GPIO12 interrupt. |
11 | GPIO11 | RW | GPIO11 interrupt. |
10 | GPIO10 | RW | GPIO10 interrupt. |
9 | GPIO9 | RW | GPIO9 interrupt. |
8 | GPIO8 | RW | GPIO8 interrupt. |
7 | GPIO7 | RW | GPIO7 interrupt. |
6 | GPIO6 | RW | GPIO6 interrupt. |
5 | GPIO5 | RW | GPIO5 interrupt. |
4 | GPIO4 | RW | GPIO4 interrupt. |
3 | GPIO3 | RW | GPIO3 interrupt. |
2 | GPIO2 | RW | GPIO2 interrupt. |
1 | GPIO1 | RW | GPIO1 interrupt. |
0 | GPIO0 | RW | GPIO0 interrupt. |
Instance 0 Address: | 0x4001020C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO31
0x0 |
GPIO30
0x0 |
GPIO29
0x0 |
GPIO28
0x0 |
GPIO27
0x0 |
GPIO26
0x0 |
GPIO25
0x0 |
GPIO24
0x0 |
GPIO23
0x0 |
GPIO22
0x0 |
GPIO21
0x0 |
GPIO20
0x0 |
GPIO19
0x0 |
GPIO18
0x0 |
GPIO17
0x0 |
GPIO16
0x0 |
GPIO15
0x0 |
GPIO14
0x0 |
GPIO13
0x0 |
GPIO12
0x0 |
GPIO11
0x0 |
GPIO10
0x0 |
GPIO9
0x0 |
GPIO8
0x0 |
GPIO7
0x0 |
GPIO6
0x0 |
GPIO5
0x0 |
GPIO4
0x0 |
GPIO3
0x0 |
GPIO2
0x0 |
GPIO1
0x0 |
GPIO0
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO31 | RW | GPIO31 interrupt. |
30 | GPIO30 | RW | GPIO30 interrupt. |
29 | GPIO29 | RW | GPIO29 interrupt. |
28 | GPIO28 | RW | GPIO28 interrupt. |
27 | GPIO27 | RW | GPIO27 interrupt. |
26 | GPIO26 | RW | GPIO26 interrupt. |
25 | GPIO25 | RW | GPIO25 interrupt. |
24 | GPIO24 | RW | GPIO24 interrupt. |
23 | GPIO23 | RW | GPIO23 interrupt. |
22 | GPIO22 | RW | GPIO22 interrupt. |
21 | GPIO21 | RW | GPIO21 interrupt. |
20 | GPIO20 | RW | GPIO20 interrupt. |
19 | GPIO19 | RW | GPIO19 interrupt. |
18 | GPIO18 | RW | GPIO18interrupt. |
17 | GPIO17 | RW | GPIO17 interrupt. |
16 | GPIO16 | RW | GPIO16 interrupt. |
15 | GPIO15 | RW | GPIO15 interrupt. |
14 | GPIO14 | RW | GPIO14 interrupt. |
13 | GPIO13 | RW | GPIO13 interrupt. |
12 | GPIO12 | RW | GPIO12 interrupt. |
11 | GPIO11 | RW | GPIO11 interrupt. |
10 | GPIO10 | RW | GPIO10 interrupt. |
9 | GPIO9 | RW | GPIO9 interrupt. |
8 | GPIO8 | RW | GPIO8 interrupt. |
7 | GPIO7 | RW | GPIO7 interrupt. |
6 | GPIO6 | RW | GPIO6 interrupt. |
5 | GPIO5 | RW | GPIO5 interrupt. |
4 | GPIO4 | RW | GPIO4 interrupt. |
3 | GPIO3 | RW | GPIO3 interrupt. |
2 | GPIO2 | RW | GPIO2 interrupt. |
1 | GPIO1 | RW | GPIO1 interrupt. |
0 | GPIO0 | RW | GPIO0 interrupt. |
Instance 0 Address: | 0x40010210 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
GPIO49
0x0 |
GPIO48
0x0 |
GPIO47
0x0 |
GPIO46
0x0 |
GPIO45
0x0 |
GPIO44
0x0 |
GPIO43
0x0 |
GPIO42
0x0 |
GPIO41
0x0 |
GPIO40
0x0 |
GPIO39
0x0 |
GPIO38
0x0 |
GPIO37
0x0 |
GPIO36
0x0 |
GPIO35
0x0 |
GPIO34
0x0 |
GPIO33
0x0 |
GPIO32
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17 | GPIO49 | RW | GPIO49 interrupt. |
16 | GPIO48 | RW | GPIO48 interrupt. |
15 | GPIO47 | RW | GPIO47 interrupt. |
14 | GPIO46 | RW | GPIO46 interrupt. |
13 | GPIO45 | RW | GPIO45 interrupt. |
12 | GPIO44 | RW | GPIO44 interrupt. |
11 | GPIO43 | RW | GPIO43 interrupt. |
10 | GPIO42 | RW | GPIO42 interrupt. |
9 | GPIO41 | RW | GPIO41 interrupt. |
8 | GPIO40 | RW | GPIO40 interrupt. |
7 | GPIO39 | RW | GPIO39 interrupt. |
6 | GPIO38 | RW | GPIO38 interrupt. |
5 | GPIO37 | RW | GPIO37 interrupt. |
4 | GPIO36 | RW | GPIO36 interrupt. |
3 | GPIO35 | RW | GPIO35 interrupt. |
2 | GPIO34 | RW | GPIO34 interrupt. |
1 | GPIO33 | RW | GPIO33 interrupt. |
0 | GPIO32 | RW | GPIO32 interrupt. |
Instance 0 Address: | 0x40010214 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
GPIO49
0x0 |
GPIO48
0x0 |
GPIO47
0x0 |
GPIO46
0x0 |
GPIO45
0x0 |
GPIO44
0x0 |
GPIO43
0x0 |
GPIO42
0x0 |
GPIO41
0x0 |
GPIO40
0x0 |
GPIO39
0x0 |
GPIO38
0x0 |
GPIO37
0x0 |
GPIO36
0x0 |
GPIO35
0x0 |
GPIO34
0x0 |
GPIO33
0x0 |
GPIO32
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17 | GPIO49 | RW | GPIO49 interrupt. |
16 | GPIO48 | RW | GPIO48 interrupt. |
15 | GPIO47 | RW | GPIO47 interrupt. |
14 | GPIO46 | RW | GPIO46 interrupt. |
13 | GPIO45 | RW | GPIO45 interrupt. |
12 | GPIO44 | RW | GPIO44 interrupt. |
11 | GPIO43 | RW | GPIO43 interrupt. |
10 | GPIO42 | RW | GPIO42 interrupt. |
9 | GPIO41 | RW | GPIO41 interrupt. |
8 | GPIO40 | RW | GPIO40 interrupt. |
7 | GPIO39 | RW | GPIO39 interrupt. |
6 | GPIO38 | RW | GPIO38 interrupt. |
5 | GPIO37 | RW | GPIO37 interrupt. |
4 | GPIO36 | RW | GPIO36 interrupt. |
3 | GPIO35 | RW | GPIO35 interrupt. |
2 | GPIO34 | RW | GPIO34 interrupt. |
1 | GPIO33 | RW | GPIO33 interrupt. |
0 | GPIO32 | RW | GPIO32 interrupt. |
Instance 0 Address: | 0x40010218 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
GPIO49
0x0 |
GPIO48
0x0 |
GPIO47
0x0 |
GPIO46
0x0 |
GPIO45
0x0 |
GPIO44
0x0 |
GPIO43
0x0 |
GPIO42
0x0 |
GPIO41
0x0 |
GPIO40
0x0 |
GPIO39
0x0 |
GPIO38
0x0 |
GPIO37
0x0 |
GPIO36
0x0 |
GPIO35
0x0 |
GPIO34
0x0 |
GPIO33
0x0 |
GPIO32
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17 | GPIO49 | RW | GPIO49 interrupt. |
16 | GPIO48 | RW | GPIO48 interrupt. |
15 | GPIO47 | RW | GPIO47 interrupt. |
14 | GPIO46 | RW | GPIO46 interrupt. |
13 | GPIO45 | RW | GPIO45 interrupt. |
12 | GPIO44 | RW | GPIO44 interrupt. |
11 | GPIO43 | RW | GPIO43 interrupt. |
10 | GPIO42 | RW | GPIO42 interrupt. |
9 | GPIO41 | RW | GPIO41 interrupt. |
8 | GPIO40 | RW | GPIO40 interrupt. |
7 | GPIO39 | RW | GPIO39 interrupt. |
6 | GPIO38 | RW | GPIO38 interrupt. |
5 | GPIO37 | RW | GPIO37 interrupt. |
4 | GPIO36 | RW | GPIO36 interrupt. |
3 | GPIO35 | RW | GPIO35 interrupt. |
2 | GPIO34 | RW | GPIO34 interrupt. |
1 | GPIO33 | RW | GPIO33 interrupt. |
0 | GPIO32 | RW | GPIO32 interrupt. |
Instance 0 Address: | 0x4001021C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
GPIO49
0x0 |
GPIO48
0x0 |
GPIO47
0x0 |
GPIO46
0x0 |
GPIO45
0x0 |
GPIO44
0x0 |
GPIO43
0x0 |
GPIO42
0x0 |
GPIO41
0x0 |
GPIO40
0x0 |
GPIO39
0x0 |
GPIO38
0x0 |
GPIO37
0x0 |
GPIO36
0x0 |
GPIO35
0x0 |
GPIO34
0x0 |
GPIO33
0x0 |
GPIO32
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17 | GPIO49 | RW | GPIO49 interrupt. |
16 | GPIO48 | RW | GPIO48 interrupt. |
15 | GPIO47 | RW | GPIO47 interrupt. |
14 | GPIO46 | RW | GPIO46 interrupt. |
13 | GPIO45 | RW | GPIO45 interrupt. |
12 | GPIO44 | RW | GPIO44 interrupt. |
11 | GPIO43 | RW | GPIO43 interrupt. |
10 | GPIO42 | RW | GPIO42 interrupt. |
9 | GPIO41 | RW | GPIO41 interrupt. |
8 | GPIO40 | RW | GPIO40 interrupt. |
7 | GPIO39 | RW | GPIO39 interrupt. |
6 | GPIO38 | RW | GPIO38 interrupt. |
5 | GPIO37 | RW | GPIO37 interrupt. |
4 | GPIO36 | RW | GPIO36 interrupt. |
3 | GPIO35 | RW | GPIO35 interrupt. |
2 | GPIO34 | RW | GPIO34 interrupt. |
1 | GPIO33 | RW | GPIO33 interrupt. |
0 | GPIO32 | RW | GPIO32 interrupt. |