Apollo Register Documentation  v2.4.2
IOMSTR - I2C/SPI Master

IOMSTR Register Index

  0x00000000:   FIFO - FIFO Access Port
  0x00000100:   FIFOPTR - Current FIFO Pointers
  0x00000104:   TLNGTH - Transfer Length
  0x00000108:   FIFOTHR - FIFO Threshold Configuration
  0x0000010C:   CLKCFG - I/O Clock Configuration
  0x00000110:   CMD - Command Register
  0x00000114:   CMDRPT - Command Repeat Register
  0x00000118:   STATUS - Status Register
  0x0000011C:   CFG - I/O Master Configuration
  0x00000200:   INTEN - IO Master Interrupts: Enable
  0x00000204:   INTSTAT - IO Master Interrupts: Status
  0x00000208:   INTCLR - IO Master Interrupts: Clear
  0x0000020C:   INTSET - IO Master Interrupts: Set
  0x00000300:   DBG0 -
  0x00000304:   DBG1 -

FIFO - FIFO Access Port

Address:

  Instance 0 Address:   0x50004000
  Instance 1 Address:   0x50005000
  Instance 2 Address:   0x50006000
  Instance 3 Address:   0x50007000
  Instance 4 Address:   0x50008000
  Instance 5 Address:   0x50009000

Description:

FIFO Access Port

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFO
0x0

Bits Name RW Description
31:0 FIFO RW FIFO access port.


FIFOPTR - Current FIFO Pointers

Address:

  Instance 0 Address:   0x50004100
  Instance 1 Address:   0x50005100
  Instance 2 Address:   0x50006100
  Instance 3 Address:   0x50007100
  Instance 4 Address:   0x50008100
  Instance 5 Address:   0x50009100

Description:

Current FIFO Pointers

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
FIFOREM
0x0
RSVD
0x0
FIFOSIZ
0x0

Bits Name RW Description
31:24 RSVD RO RESERVED

23:16 FIFOREM RO The number of bytes remaining in the FIFO (i.e. 128-FIFOSIZ).

15:8 RSVD RO RESERVED

7:0 FIFOSIZ RO The number of bytes currently in the FIFO.


TLNGTH - Transfer Length

Address:

  Instance 0 Address:   0x50004104
  Instance 1 Address:   0x50005104
  Instance 2 Address:   0x50006104
  Instance 3 Address:   0x50007104
  Instance 4 Address:   0x50008104
  Instance 5 Address:   0x50009104

Description:

Transfer Length

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
TLNGTH
0x0

Bits Name RW Description
31:12 RSVD RO RESERVED

11:0 TLNGTH RO Remaining transfer length.


FIFOTHR - FIFO Threshold Configuration

Address:

  Instance 0 Address:   0x50004108
  Instance 1 Address:   0x50005108
  Instance 2 Address:   0x50006108
  Instance 3 Address:   0x50007108
  Instance 4 Address:   0x50008108
  Instance 5 Address:   0x50009108

Description:

FIFO Threshold Configuration

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
FIFOWTHR
0x0
RSVD
0x0
FIFORTHR
0x0

Bits Name RW Description
31:15 RSVD RO RESERVED

14:8 FIFOWTHR RW FIFO write threshold.

7 RSVD RO RESERVED

6:0 FIFORTHR RW FIFO read threshold.


CLKCFG - I/O Clock Configuration

Address:

  Instance 0 Address:   0x5000410C
  Instance 1 Address:   0x5000510C
  Instance 2 Address:   0x5000610C
  Instance 3 Address:   0x5000710C
  Instance 4 Address:   0x5000810C
  Instance 5 Address:   0x5000910C

Description:

I/O Clock Configuration

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOTPER
0x0
LOWPER
0x0
RSVD
0x0
DIVEN
0x0
DIV3
0x0
FSEL
0x0
RSVD
0x0

Bits Name RW Description
31:24 TOTPER RW Clock total count minus 1.

23:16 LOWPER RW Clock low count minus 1.

15:13 RSVD RO RESERVED

12 DIVEN RW Enable clock division by TOTPER.

DIS = 0x0 - Disable TOTPER division.
EN = 0x1 - Enable TOTPER division.
11 DIV3 RW Enable divide by 3.

DIS = 0x0 - Select divide by 1.
EN = 0x1 - Select divide by 3.
10:8 FSEL RW Select the input clock frequency.

HFRC_DIV64 = 0x0 - Selects the HFRC / 64 as the input clock.
HFRC = 0x1 - Selects the HFRC as the input clock.
HFRC_DIV2 = 0x2 - Selects the HFRC / 2 as the input clock.
HFRC_DIV4 = 0x3 - Selects the HFRC / 4 as the input clock.
HFRC_DIV8 = 0x4 - Selects the HFRC / 8 as the input clock.
HFRC_DIV16 = 0x5 - Selects the HFRC / 16 as the input clock.
HFRC_DIV32 = 0x6 - Selects the HFRC / 32 as the input clock.
RSVD = 0x7 - Reserved.
7:0 RSVD RO RESERVED


CMD - Command Register

Address:

  Instance 0 Address:   0x50004110
  Instance 1 Address:   0x50005110
  Instance 2 Address:   0x50006110
  Instance 3 Address:   0x50007110
  Instance 4 Address:   0x50008110
  Instance 5 Address:   0x50009110

Description:

Command Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMD
0x0

Bits Name RW Description
31:0 CMD RW This register is the I/O Command. The command fields are as follow:

POS_LENGTH = 0x0 - LSB bit position of the CMD LENGTH field.
POS_OFFSET = 0x8 - LSB bit position of the CMD OFFSET field.
POS_ADDRESS = 0x16 - LSB bit position of the I2C CMD ADDRESS field.
POS_CHNL = 0x16 - LSB bit position of the SPI CMD CHANNEL field.
POS_UPLNGTH = 0x23 - LSB bit position of the SPI CMD UPLNGTH field.
POS_10BIT = 0x26 - LSB bit position of the I2C CMD 10-bit field.
POS_LSB = 0x27 - LSB bit position of the CMD LSB-first field.
POS_CONT = 0x28 - LSB bit position of the CMD CONTinue field.
POS_OPER = 0x29 - LSB bit position of the CMD OPERation field.
MSK_LENGTH = 0xFF - LSB bit mask of the CMD LENGTH field.
MSK_OFFSET = 0xFF00 - LSB bit mask of the CMD OFFSET field.
MSK_ADDRESS = 0xFF0000 - LSB bit mask of the I2C CMD ADDRESS field.
MSK_CHNL = 0x70000 - LSB bit mask of the SPI CMD CHANNEL field.
MSK_UPLNGTH = 0x7800000 - LSB bit mask of the SPI CMD UPLNGTH field.
MSK_10BIT = 0x4000000 - LSB bit mask of the I2C CMD 10-bit field.
MSK_LSB = 0x8000000 - LSB bit mask of the CMD LSB-first field.
MSK_CONT = 0x10000000 - LSB bit mask of the CMD CONTinue field.
MSK_OPER = 0xE0000000 - LSB bit mask of the CMD OPERation field.

CMDRPT - Command Repeat Register

Address:

  Instance 0 Address:   0x50004114
  Instance 1 Address:   0x50005114
  Instance 2 Address:   0x50006114
  Instance 3 Address:   0x50007114
  Instance 4 Address:   0x50008114
  Instance 5 Address:   0x50009114

Description:

Command Repeat Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CMDRPT
0x0

Bits Name RW Description
31:5 RSVD RO RESERVED

4:0 CMDRPT RW These bits hold the Command repeat count.


STATUS - Status Register

Address:

  Instance 0 Address:   0x50004118
  Instance 1 Address:   0x50005118
  Instance 2 Address:   0x50006118
  Instance 3 Address:   0x50007118
  Instance 4 Address:   0x50008118
  Instance 5 Address:   0x50009118

Description:

Status Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
IDLEST
0x0
CMDACT
0x0
ERR
0x0

Bits Name RW Description
31:3 RSVD RO RESERVED

2 IDLEST RO This bit indicates if the I/O state machine is IDLE.

IDLE = 0x1 - The I/O state machine is in the idle state.
1 CMDACT RO This bit indicates if the I/O Command is active.

ACTIVE = 0x1 - An I/O command is active.
0 ERR RO This bit indicates if an error interrupt has occurred.

ERROR = 0x1 - An error has been indicated by the IOM.

CFG - I/O Master Configuration

Address:

  Instance 0 Address:   0x5000411C
  Instance 1 Address:   0x5000511C
  Instance 2 Address:   0x5000611C
  Instance 3 Address:   0x5000711C
  Instance 4 Address:   0x5000811C
  Instance 5 Address:   0x5000911C

Description:

I/O Master Configuration

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IFCEN
0x0
RSVD
0x0
RDFCPOL
0x0
WTFCPOL
0x1
WTFCIRQ
0x0
FCDEL
0x0
MOSIINV
0x0
RDFC
0x0
WTFC
0x0
RSVD
0x0
STARTRD
0x0
FULLDUP
0x0
SPHA
0x0
SPOL
0x0
IFCSEL
0x0

Bits Name RW Description
31 IFCEN RW This bit enables the IO Master.

DIS = 0x0 - Disable the IO Master.
EN = 0x1 - Enable the IO Master.
30:15 RSVD RO RESERVED

14 RDFCPOL RW This bit selects the read flow control signal polarity.

HIGH = 0x0 - Flow control signal high creates flow control.
LOW = 0x1 - Flow control signal low creates flow control.
13 WTFCPOL RW This bit selects the write flow control signal polarity.

HIGH = 0x0 - Flow control signal high creates flow control.
LOW = 0x1 - Flow control signal low creates flow control.
12 WTFCIRQ RW This bit selects the write mode flow control signal.

MISO = 0x0 - MISO is used as the write mode flow control signal.
IRQ = 0x1 - IRQ is used as the write mode flow control signal.
11 FCDEL RW This bit enables a pause cycle in flow control mode.

DIS = 0x0 - No pause cycle is inserted.
EN = 0x1 - One pause cycle is inserted.
10 MOSIINV RW This bit invewrts MOSI when flow control is enabled.

NORMAL = 0x0 - MOSI is set to 0 in read mode and 1 in write mode.
INVERT = 0x1 - MOSI is set to 1 in read mode and 0 in write mode.
9 RDFC RW This bit enables read mode flow control.

DIS = 0x0 - Read mode flow control disabled.
EN = 0x1 - Read mode flow control enabled.
8 WTFC RW This bit enables write mode flow control.

DIS = 0x0 - Write mode flow control disabled.
EN = 0x1 - Write mode flow control enabled.
7:6 RSVD RO RESERVED

5:4 STARTRD RW This bit selects the preread timing.

PRERD0 = 0x0 - 0 read delay cycles.
PRERD1 = 0x1 - 1 read delay cycles.
PRERD2 = 0x2 - 2 read delay cycles.
PRERD3 = 0x3 - 3 read delay cycles.
3 FULLDUP RW This bit selects full duplex mode.

NORMAL = 0x0 - 128 byte FIFO in half duplex mode.
FULLDUP = 0x1 - 64 byte FIFO in full duplex mode.
2 SPHA RW This bit selects SPI phase.

SAMPLE_LEADING_EDGE = 0x0 - Sample on the leading (first) clock edge.
SAMPLE_TRAILING_EDGE = 0x1 - Sample on the trailing (second) clock edge.
1 SPOL RW This bit selects SPI polarity.

CLK_BASE_0 = 0x0 - The base value of the clock is 0.
CLK_BASE_1 = 0x1 - The base value of the clock is 1.
0 IFCSEL RW This bit selects the I/O interface.

I2C = 0x0 - Selects I2C interface for the I/O Master.
SPI = 0x1 - Selects SPI interface for the I/O Master.

INTEN - IO Master Interrupts: Enable

Address:

  Instance 0 Address:   0x50004200
  Instance 1 Address:   0x50005200
  Instance 2 Address:   0x50006200
  Instance 3 Address:   0x50007200
  Instance 4 Address:   0x50008200
  Instance 5 Address:   0x50009200

Description:

Set bits in this register to allow this module to generate the corresponding interrupt.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ARB
0x0
STOP
0x0
START
0x0
ICMD
0x0
IACC
0x0
WTLEN
0x0
NAK
0x0
FOVFL
0x0
FUNDFL
0x0
THR
0x0
CMDCMP
0x0

Bits Name RW Description
31:11 RSVD RO RESERVED

10 ARB RW This is the arbitration loss interrupt.

9 STOP RW This is the STOP command interrupt.

8 START RW This is the START command interrupt.

7 ICMD RW This is the illegal command interrupt.

6 IACC RW This is the illegal FIFO access interrupt.

5 WTLEN RW This is the write length mismatch interrupt.

4 NAK RW This is the I2C NAK interrupt.

3 FOVFL RW This is the Read FIFO Overflow interrupt.

2 FUNDFL RW This is the Write FIFO Underflow interrupt.

1 THR RW This is the FIFO Threshold interrupt.

0 CMDCMP RW This is the Command Complete interrupt.


INTSTAT - IO Master Interrupts: Status

Address:

  Instance 0 Address:   0x50004204
  Instance 1 Address:   0x50005204
  Instance 2 Address:   0x50006204
  Instance 3 Address:   0x50007204
  Instance 4 Address:   0x50008204
  Instance 5 Address:   0x50009204

Description:

Read bits from this register to discover the cause of a recent interrupt.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ARB
0x0
STOP
0x0
START
0x0
ICMD
0x0
IACC
0x0
WTLEN
0x0
NAK
0x0
FOVFL
0x0
FUNDFL
0x0
THR
0x0
CMDCMP
0x0

Bits Name RW Description
31:11 RSVD RO RESERVED

10 ARB RW This is the arbitration loss interrupt.

9 STOP RW This is the STOP command interrupt.

8 START RW This is the START command interrupt.

7 ICMD RW This is the illegal command interrupt.

6 IACC RW This is the illegal FIFO access interrupt.

5 WTLEN RW This is the write length mismatch interrupt.

4 NAK RW This is the I2C NAK interrupt.

3 FOVFL RW This is the Read FIFO Overflow interrupt.

2 FUNDFL RW This is the Write FIFO Underflow interrupt.

1 THR RW This is the FIFO Threshold interrupt.

0 CMDCMP RW This is the Command Complete interrupt.


INTCLR - IO Master Interrupts: Clear

Address:

  Instance 0 Address:   0x50004208
  Instance 1 Address:   0x50005208
  Instance 2 Address:   0x50006208
  Instance 3 Address:   0x50007208
  Instance 4 Address:   0x50008208
  Instance 5 Address:   0x50009208

Description:

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ARB
0x0
STOP
0x0
START
0x0
ICMD
0x0
IACC
0x0
WTLEN
0x0
NAK
0x0
FOVFL
0x0
FUNDFL
0x0
THR
0x0
CMDCMP
0x0

Bits Name RW Description
31:11 RSVD RO RESERVED

10 ARB RW This is the arbitration loss interrupt.

9 STOP RW This is the STOP command interrupt.

8 START RW This is the START command interrupt.

7 ICMD RW This is the illegal command interrupt.

6 IACC RW This is the illegal FIFO access interrupt.

5 WTLEN RW This is the write length mismatch interrupt.

4 NAK RW This is the I2C NAK interrupt.

3 FOVFL RW This is the Read FIFO Overflow interrupt.

2 FUNDFL RW This is the Write FIFO Underflow interrupt.

1 THR RW This is the FIFO Threshold interrupt.

0 CMDCMP RW This is the Command Complete interrupt.


INTSET - IO Master Interrupts: Set

Address:

  Instance 0 Address:   0x5000420C
  Instance 1 Address:   0x5000520C
  Instance 2 Address:   0x5000620C
  Instance 3 Address:   0x5000720C
  Instance 4 Address:   0x5000820C
  Instance 5 Address:   0x5000920C

Description:

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ARB
0x0
STOP
0x0
START
0x0
ICMD
0x0
IACC
0x0
WTLEN
0x0
NAK
0x0
FOVFL
0x0
FUNDFL
0x0
THR
0x0
CMDCMP
0x0

Bits Name RW Description
31:11 RSVD RO RESERVED

10 ARB RW This is the arbitration loss interrupt.

9 STOP RW This is the STOP command interrupt.

8 START RW This is the START command interrupt.

7 ICMD RW This is the illegal command interrupt.

6 IACC RW This is the illegal FIFO access interrupt.

5 WTLEN RW This is the write length mismatch interrupt.

4 NAK RW This is the I2C NAK interrupt.

3 FOVFL RW This is the Read FIFO Overflow interrupt.

2 FUNDFL RW This is the Write FIFO Underflow interrupt.

1 THR RW This is the FIFO Threshold interrupt.

0 CMDCMP RW This is the Command Complete interrupt.


DBG0 -

Address:

  Instance 0 Address:   0x50004300
  Instance 1 Address:   0x50005300
  Instance 2 Address:   0x50006300
  Instance 3 Address:   0x50007300
  Instance 4 Address:   0x50008300
  Instance 5 Address:   0x50009300

Description:

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG0
0x0

Bits Name RW Description
31:0 DBG0 RO


DBG1 -

Address:

  Instance 0 Address:   0x50004304
  Instance 1 Address:   0x50005304
  Instance 2 Address:   0x50006304
  Instance 3 Address:   0x50007304
  Instance 4 Address:   0x50008304
  Instance 5 Address:   0x50009304

Description:

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG1
0x0

Bits Name RW Description
31:0 DBG1 RO