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Apollo Register Documentation v2.4.2
|
Instance 0 Address: | 0x40010000 |
This register controls the pad configuration controls for PAD3 through PAD0. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PAD3PWRUP
0x0 |
RSVD
0x0 |
PAD3FNCSEL
0x3 |
PAD3STRNG
0x0 |
PAD3INPEN
0x0 |
PAD3PULL
0x0 |
RSVD
0x0 |
PAD2FNCSEL
0x3 |
PAD2STRNG
0x0 |
PAD2INPEN
0x0 |
PAD2PULL
0x0 |
RSVD
0x0 |
PAD1FNCSEL
0x3 |
PAD1STRNG
0x0 |
PAD1INPEN
0x0 |
PAD1PULL
0x0 |
RSVD
0x0 |
PAD0FNCSEL
0x3 |
PAD0STRNG
0x0 |
PAD0INPEN
0x0 |
PAD0PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | PAD3PWRUP | RW | Pad 3 upper power switch enable DIS = 0x0 - Power switch disabled EN = 0x1 - Power switch enabled |
30 | RSVD | RO | RESERVED |
29:27 | PAD3FNCSEL | RW | Pad 3 function select TRIG0 = 0x0 - Configure as the ADC Trigger 0 signal SLnCE = 0x1 - Configure as the IOSLAVE SPI nCE signal M1nCE4 = 0x2 - Configure as the SPI channel 4 nCE signal from IOMSTR1 GPIO3 = 0x3 - Configure as GPIO3 M0nCE = 0x4 - Configure as the IOSLAVE SPI nCE loopback signal from IOMSTR0 M1nCE = 0x5 - Configure as the IOSLAVE SPI nCE loopback signal from IOMSTR1 DIS = 0x6 - Pad disabled |
26 | PAD3STRNG | RW | Pad 3 drive strength. LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD3INPEN | RW | Pad 3 input enable. DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD3PULL | RW | Pad 3 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:22 | RSVD | RO | RESERVED |
21:19 | PAD2FNCSEL | RW | Pad 2 function select SLWIR3 = 0x0 - Configure as the IOSLAVE SPI 3-wire MOSI/MISO signal SLMOSI = 0x1 - Configure as the IOSLAVE SPI MOSI signal CLKOUT = 0x2 - Configure as the CLKOUT signal GPIO2 = 0x3 - Configure as GPIO2 M0MOSI = 0x4 - Configure as the IOSLAVE SPI MOSI loopback signal from IOMSTR0 M1MOSI = 0x5 - Configure as the IOSLAVE SPI MOSI loopback signal from IOMSTR1 M0WIR3 = 0x6 - Configure as the IOSLAVE SPI 3-wire MOSI/MISO loopback signal from IOMSTR0 M1WIR3 = 0x7 - Configure as the IOSLAVE SPI 3-wire MOSI/MISO loopback signal from IOMSTR1 |
18 | PAD2STRNG | RW | Pad 2 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD2INPEN | RW | Pad 2 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD2PULL | RW | Pad 2 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:14 | RSVD | RO | RESERVED |
13:11 | PAD1FNCSEL | RW | Pad 1 function select SLSDA = 0x0 - Configure as the IOSLAVE I2C SDA signal SLMISO = 0x1 - Configure as the IOSLAVE SPI MISO signal UARTRX = 0x2 - Configure as the UART RX signal GPIO1 = 0x3 - Configure as GPIO1 M0MISO = 0x4 - Configure as the IOSLAVE SPI MISO loopback signal from IOMSTR0 M1MISO = 0x5 - Configure as the IOSLAVE SPI MISO loopback signal from IOMSTR1 M0SDA = 0x6 - Configure as the IOSLAVE I2C SDA loopback signal from IOMSTR0 M1SDA = 0x7 - Configure as the IOSLAVE I2C SDA loopback signal from IOMSTR1 |
10 | PAD1STRNG | RW | Pad 1 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD1INPEN | RW | Pad 1 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD1PULL | RW | Pad 1 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:6 | RSVD | RO | RESERVED |
5:3 | PAD0FNCSEL | RW | Pad 0 function select SLSCL = 0x0 - Configure as the IOSLAVE I2C SCL signal SLSCK = 0x1 - Configure as the IOSLAVE SPI SCK signal UARTTX = 0x2 - Configure as the UART TX signal GPIO0 = 0x3 - Configure as GPIO0 M0SCK = 0x4 - Configure as the IOSLAVE SPI SCK loopback signal from IOMSTR0 M1SCK = 0x5 - Configure as the IOSLAVE SPI SCK loopback signal from IOMSTR1 M0SCL = 0x6 - Configure as the IOSLAVE I2C SCL loopback signal from IOMSTR0 M1SCL = 0x7 - Configure as the IOSLAVE I2C SCL loopback signal from IOMSTR1 |
2 | PAD0STRNG | RW | Pad 0 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD0INPEN | RW | Pad 0 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD0PULL | RW | Pad 0 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x40010004 |
This register controls the pad configuration controls for PAD7 through PAD4. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD7FNCSEL
0x3 |
PAD7STRNG
0x0 |
PAD7INPEN
0x0 |
PAD7PULL
0x0 |
PAD6RSEL
0x0 |
PAD6FNCSEL
0x3 |
PAD6STRNG
0x0 |
PAD6INPEN
0x0 |
PAD6PULL
0x0 |
PAD5RSEL
0x0 |
PAD5FNCSEL
0x3 |
PAD5STRNG
0x0 |
PAD5INPEN
0x0 |
PAD5PULL
0x0 |
PAD4PWRUP
0x0 |
RSVD
0x0 |
PAD4FNCSEL
0x3 |
PAD4STRNG
0x0 |
PAD4INPEN
0x0 |
PAD4PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:30 | RSVD | RO | RESERVED |
29:27 | PAD7FNCSEL | RW | Pad 7 function select M0WIR3 = 0x0 - Configure as the IOMSTR0 SPI 3-wire MOSI/MISO signal M0MOSI = 0x1 - Configure as the IOMSTR0 SPI MOSI signal CLKOUT = 0x2 - Configure as the CLKOUT signal GPIO7 = 0x3 - Configure as GPIO7 SLWIR3 = 0x6 - Configure as the IOMSTR0 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE DIS = 0x7 - Pad disabled |
26 | PAD7STRNG | RW | Pad 7 drive strentgh LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD7INPEN | RW | Pad 7 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD7PULL | RW | Pad 7 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:22 | PAD6RSEL | RW | Pad 6 pullup resistor selection. PULL1_5K = 0x0 - Pullup is ~1.5 KOhms PULL6K = 0x1 - Pullup is ~6 KOhms PULL12K = 0x2 - Pullup is ~12 KOhms PULL24K = 0x3 - Pullup is ~24 KOhms |
21:19 | PAD6FNCSEL | RW | Pad 6 function select M0SDA = 0x0 - Configure as the IOMSTR0 I2C SDA signal M0MISO = 0x1 - Configure as the IOMSTR0 SPI MISO signal UACTS = 0x2 - Configure as the UART CTS signal GPIO6 = 0x3 - Configure as GPIO6 SLMISO = 0x4 - Configure as the IOMSTR0 SPI MISO loopback signal from IOSLAVE SLSDA = 0x6 - Configure as the IOMSTR0 I2C SDA loopback signal from IOSLAVE DIS = 0x7 - Pad disabled |
18 | PAD6STRNG | RW | Pad 6 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD6INPEN | RW | Pad 6 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD6PULL | RW | Pad 6 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:14 | PAD5RSEL | RW | Pad 5 pullup resistor selection. PULL1_5K = 0x0 - Pullup is ~1.5 KOhms PULL6K = 0x1 - Pullup is ~6 KOhms PULL12K = 0x2 - Pullup is ~12 KOhms PULL24K = 0x3 - Pullup is ~24 KOhms |
13:11 | PAD5FNCSEL | RW | Pad 5 function select M0SCL = 0x0 - Configure as the IOMSTR0 I2C SCL signal M0SCK = 0x1 - Configure as the IOMSTR0 SPI SCK signal UARTS = 0x2 - Configure as the UART RTS signal GPIO5 = 0x3 - Configure as GPIO5 SLSCK = 0x4 - Configure as the IOMSTR0 SPI SCK loopback signal from IOSLAVE SLSCL = 0x6 - Configure as the IOMSTR0 I2C SCL loopback signal from IOSLAVE DIS = 0x7 - Pad disabled |
10 | PAD5STRNG | RW | Pad 5 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD5INPEN | RW | Pad 5 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD5PULL | RW | Pad 5 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7 | PAD4PWRUP | RW | Pad 4 upper power switch enable DIS = 0x0 - Power switch disabled EN = 0x1 - Power switch enabled |
6 | RSVD | RO | RESERVED |
5:3 | PAD4FNCSEL | RW | Pad 4 function select TRIG1 = 0x0 - Configure as the ADC Trigger 1 signal SLINT = 0x1 - Configure as the IOSLAVE interrupt out signal M0nCE5 = 0x2 - Configure as the SPI channel 5 nCE signal from IOMSTR0 GPIO4 = 0x3 - Configure as GPIO4 SLINTGP = 0x4 - Configure as the IOSLAVE interrupt loopback signal to GPIO4 SWO = 0x5 - Configure as the serial wire debug SWO signal CLKOUT = 0x6 - Configure as the CLKOUT signal DIS = 0x7 - Pad disabled |
2 | PAD4STRNG | RW | Pad 4 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD4INPEN | RW | Pad 4 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD4PULL | RW | Pad 4 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x40010008 |
This register controls the pad configuration controls for PAD11 through PAD8. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD11PWRDN
0x0 |
RSVD
0x0 |
PAD11FNCSEL
0x3 |
PAD11STRNG
0x0 |
PAD11INPEN
0x0 |
PAD11PULL
0x0 |
RSVD
0x0 |
PAD10FNCSEL
0x3 |
PAD10STRNG
0x0 |
PAD10INPEN
0x0 |
PAD10PULL
0x0 |
PAD9RSEL
0x0 |
PAD9FNCSEL
0x3 |
PAD9STRNG
0x0 |
PAD9INPEN
0x0 |
PAD9PULL
0x0 |
PAD8RSEL
0x0 |
PAD8FNCSEL
0x3 |
PAD8STRNG
0x0 |
PAD8INPEN
0x0 |
PAD8PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | RSVD | RO | RESERVED |
30 | PAD11PWRDN | RW | Pad 11 lower power switch enable DIS = 0x0 - Power switch disabled EN = 0x1 - Power switch enabled |
29 | RSVD | RO | RESERVED |
28:27 | PAD11FNCSEL | RW | Pad 11 function select ANATST = 0x0 - Configure as the analog test output signal M0nCE0 = 0x1 - Configure as the SPI channel 0 nCE signal from IOMSTR0 CLKOUT = 0x2 - Configure as the CLKOUT signal GPIO11 = 0x3 - Configure as GPIO11 |
26 | PAD11STRNG | RW | Pad 11 drive strentgh LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD11INPEN | RW | Pad 11 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD11PULL | RW | Pad 11 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:22 | RSVD | RO | RESERVED |
21:19 | PAD10FNCSEL | RW | Pad 10 function select M1WIR3 = 0x0 - Configure as the IOMSTR1 SPI 3-wire MOSI/MISO signal M1MOSI = 0x1 - Configure as the IOMSTR1 SPI MOSI signal M0nCE6 = 0x2 - Configure as the SPI channel 6 nCE signal from IOMSTR0 GPIO10 = 0x3 - Configure as GPIO10 EXTHFA = 0x5 - Configure as the external HFRC A clock signal DIS = 0x6 - Pad disabled SLWIR3 = 0x7 - Configure as the IOMSTR1 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE |
18 | PAD10STRNG | RW | Pad 10 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD10INPEN | RW | Pad 10 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD10PULL | RW | Pad 10 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:14 | PAD9RSEL | RW | Pad 9 pullup resistor selection PULL1_5K = 0x0 - Pullup is ~1.5 KOhms PULL6K = 0x1 - Pullup is ~6 KOhms PULL12K = 0x2 - Pullup is ~12 KOhms PULL24K = 0x3 - Pullup is ~24 KOhms |
13:11 | PAD9FNCSEL | RW | Pad 9 function select M1SDA = 0x0 - Configure as the IOMSTR1 I2C SDA signal M1MISO = 0x1 - Configure as the IOMSTR1 SPI MISO signal M0nCE5 = 0x2 - Configure as the SPI channel 5 nCE signal from IOMSTR0 GPIO9 = 0x3 - Configure as GPIO9 SLMISO = 0x5 - Configure as the IOMSTR1 SPI MISO loopback signal from IOSLAVE DIS = 0x6 - Pad disabled SLSDA = 0x7 - Configure as the IOMSTR1 I2C SDA loopback signal from IOSLAVE |
10 | PAD9STRNG | RW | Pad 9 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD9INPEN | RW | Pad 9 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD9PULL | RW | Pad 9 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:6 | PAD8RSEL | RW | Pad 8 pullup resistor selection. PULL1_5K = 0x0 - Pullup is ~1.5 KOhms PULL6K = 0x1 - Pullup is ~6 KOhms PULL12K = 0x2 - Pullup is ~12 KOhms PULL24K = 0x3 - Pullup is ~24 KOhms |
5:3 | PAD8FNCSEL | RW | Pad 8 function select M1SCL = 0x0 - Configure as the IOMSTR1 I2C SCL signal M1SCK = 0x1 - Configure as the IOMSTR1 SPI SCK signal M0nCE4 = 0x2 - Configure as the SPI channel 4 nCE signal from IOMSTR0 GPIO8 = 0x3 - Configure as GPIO8 SLSCK = 0x5 - Configure as the IOMSTR1 SPI SCK loopback signal from IOSLAVE DIS = 0x6 - Pad disabled SLSCL = 0x7 - Configure as the IOMSTR1 I2C SCL loopback signal from IOSLAVE |
2 | PAD8STRNG | RW | Pad 8 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD8INPEN | RW | Pad 8 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD8PULL | RW | Pad 8 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x4001000C |
This register controls the pad configuration controls for PAD15 through PAD12. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD15FNCSEL
0x3 |
PAD15STRNG
0x0 |
PAD15INPEN
0x0 |
PAD15PULL
0x0 |
RSVD
0x0 |
PAD14FNCSEL
0x3 |
PAD14STRNG
0x0 |
PAD14INPEN
0x0 |
PAD14PULL
0x0 |
RSVD
0x0 |
PAD13FNCSEL
0x3 |
PAD13STRNG
0x0 |
PAD13INPEN
0x0 |
PAD13PULL
0x0 |
RSVD
0x0 |
PAD12FNCSEL
0x3 |
PAD12STRNG
0x0 |
PAD12INPEN
0x0 |
PAD12PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:30 | RSVD | RO | RESERVED |
29:27 | PAD15FNCSEL | RW | Pad 15 function select ADC3 = 0x0 - Configure as the analog ADC input 3 M1nCE3 = 0x1 - Configure as the SPI channel 3 nCE signal from IOMSTR1 UARTRX = 0x2 - Configure as the UART RX signal GPIO15 = 0x3 - Configure as GPIO15 EXTXT = 0x5 - Configure as the external XT clock signal DIS = 0x7 - Pad disabled |
26 | PAD15STRNG | RW | Pad 15 drive strentgh LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD15INPEN | RW | Pad 15 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD15PULL | RW | Pad 15 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:22 | RSVD | RO | RESERVED |
21:19 | PAD14FNCSEL | RW | Pad 14 function select ADC2 = 0x0 - Configure as the analog ADC input 2 M1nCE2 = 0x1 - Configure as the SPI channel 2 nCE signal from IOMSTR1 UARTTX = 0x2 - Configure as the UART TX signal GPIO14 = 0x3 - Configure as GPIO14 EXTHFS = 0x5 - Configure as the external HFRC select signal DIS = 0x7 - Pad disabled |
18 | PAD14STRNG | RW | Pad 14 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD14INPEN | RW | Pad 14 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD14PULL | RW | Pad 14 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:14 | RSVD | RO | RESERVED |
13:11 | PAD13FNCSEL | RW | Pad 13 function select ADC1 = 0x0 - Configure as the analog ADC input 1 M1nCE1 = 0x1 - Configure as the SPI channel 1 nCE signal from IOMSTR1 TCTB0 = 0x2 - Configure as the input/output signal from CTIMER B0 GPIO13 = 0x3 - Configure as GPIO13 EXTHFA = 0x5 - Configure as the external HFRC B clock signal SWO = 0x6 - Configure as the serial wire debug SWO signal DIS = 0x7 - Pad disabled |
10 | PAD13STRNG | RW | Pad 13 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD13INPEN | RW | Pad 13 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD13PULL | RW | Pad 13 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:5 | RSVD | RO | RESERVED |
4:3 | PAD12FNCSEL | RW | Pad 12 function select ADC0 = 0x0 - Configure as the analog ADC input 0 M1nCE0 = 0x1 - Configure as the SPI channel 0 nCE signal from IOMSTR1 TCTA0 = 0x2 - Configure as the input/output signal from CTIMER A0 GPIO12 = 0x3 - Configure as GPIO12 |
2 | PAD12STRNG | RW | Pad 12 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD12INPEN | RW | Pad 12 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD12PULL | RW | Pad 12 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x40010010 |
This register controls the pad configuration controls for PAD19 through PAD16. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD19FNCSEL
0x3 |
PAD19STRNG
0x0 |
PAD19INPEN
0x0 |
PAD19PULL
0x0 |
RSVD
0x0 |
PAD18FNCSEL
0x3 |
PAD18STRNG
0x0 |
PAD18INPEN
0x0 |
PAD18PULL
0x0 |
RSVD
0x0 |
PAD17FNCSEL
0x3 |
PAD17STRNG
0x0 |
PAD17INPEN
0x0 |
PAD17PULL
0x0 |
RSVD
0x0 |
PAD16FNCSEL
0x3 |
PAD16STRNG
0x0 |
PAD16INPEN
0x0 |
PAD16PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28:27 | PAD19FNCSEL | RW | Pad 19 function select CMPRF = 0x0 - Configure as the analog comparator reference signal M0nCE3 = 0x1 - Configure as the SPI channel 3 nCE signal from IOMSTR0 TCTB1 = 0x2 - Configure as the input/output signal from CTIMER B1 GPIO19 = 0x3 - Configure as GPIO19 |
26 | PAD19STRNG | RW | Pad 19 drive strentgh LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD19INPEN | RW | Pad 19 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD19PULL | RW | Pad 19 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:21 | RSVD | RO | RESERVED |
20:19 | PAD18FNCSEL | RW | Pad 18 function select CMPIN1 = 0x0 - Configure as the analog comparator input 1 signal M0nCE2 = 0x1 - Configure as the SPI channel 2 nCE signal from IOMSTR0 TCTA1 = 0x2 - Configure as the input/output signal from CTIMER A1 GPIO18 = 0x3 - Configure as GPIO18 |
18 | PAD18STRNG | RW | Pad 18 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD18INPEN | RW | Pad 18 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD18PULL | RW | Pad 18 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:14 | RSVD | RO | RESERVED |
13:11 | PAD17FNCSEL | RW | Pad 17 function select CMPIN0 = 0x0 - Configure as the analog comparator input 0 signal M0nCE1 = 0x1 - Configure as the SPI channel 1 nCE signal from IOMSTR0 TRIG3 = 0x2 - Configure as the ADC Trigger 3 signal GPIO17 = 0x3 - Configure as GPIO17 EXTLF = 0x5 - Configure as the external LFRC clock signal DIS = 0x7 - Pad disabled |
10 | PAD17STRNG | RW | Pad 17 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD17INPEN | RW | Pad 17 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD17PULL | RW | Pad 17 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:5 | RSVD | RO | RESERVED |
4:3 | PAD16FNCSEL | RW | Pad 16 function select ADCREF = 0x0 - Configure as the analog ADC reference input signal M0nCE4 = 0x1 - Configure as the SPI channel 4 nCE signal from IOMSTR0 TRIG2 = 0x2 - Configure as the ADC Trigger 2 signal GPIO16 = 0x3 - Configure as GPIO16 |
2 | PAD16STRNG | RW | Pad 16 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD16INPEN | RW | Pad 16 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD16PULL | RW | Pad 16 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x40010014 |
This register controls the pad configuration controls for PAD23 through PAD20. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD23FNCSEL
0x3 |
PAD23STRNG
0x0 |
PAD23INPEN
0x0 |
PAD23PULL
0x0 |
RSVD
0x0 |
PAD22FNCSEL
0x3 |
PAD22STRNG
0x0 |
PAD22INPEN
0x0 |
PAD22PULL
0x0 |
RSVD
0x0 |
PAD21FNCSEL
0x0 |
PAD21STRNG
0x0 |
PAD21INPEN
0x1 |
PAD21PULL
0x0 |
RSVD
0x0 |
PAD20FNCSEL
0x0 |
PAD20STRNG
0x0 |
PAD20INPEN
0x1 |
PAD20PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28:27 | PAD23FNCSEL | RW | Pad 23 function select UARTRX = 0x0 - Configure as the UART RX signal M0nCE0 = 0x1 - Configure as the SPI channel 0 nCE signal from IOMSTR0 TCTB3 = 0x2 - Configure as the input/output signal from CTIMER B3 GPIO23 = 0x3 - Configure as GPIO23 |
26 | PAD23STRNG | RW | Pad 23 drive strentgh LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD23INPEN | RW | Pad 23 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD23PULL | RW | Pad 23 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:21 | RSVD | RO | RESERVED |
20:19 | PAD22FNCSEL | RW | Pad 22 function select UARTTX = 0x0 - Configure as the UART TX signal M1nCE7 = 0x1 - Configure as the SPI channel 7 nCE signal from IOMSTR1 TCTA3 = 0x2 - Configure as the input/output signal from CTIMER A3 GPIO22 = 0x3 - Configure as GPIO22 |
18 | PAD22STRNG | RW | Pad 22 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD22INPEN | RW | Pad 22 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD22PULL | RW | Pad 22 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:13 | RSVD | RO | RESERVED |
12:11 | PAD21FNCSEL | RW | Pad 21 function select SWDIO = 0x0 - Configure as the serial wire debug data signal M1nCE6 = 0x1 - Configure as the SPI channel 6 nCE signal from IOMSTR1 TCTB2 = 0x2 - Configure as the input/output signal from CTIMER B2 GPIO21 = 0x3 - Configure as GPIO21 |
10 | PAD21STRNG | RW | Pad 21 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD21INPEN | RW | Pad 21 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD21PULL | RW | Pad 21 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:5 | RSVD | RO | RESERVED |
4:3 | PAD20FNCSEL | RW | Pad 20 function select SWDCK = 0x0 - Configure as the serial wire debug clock signal M1nCE5 = 0x1 - Configure as the SPI channel 5 nCE signal from IOMSTR1 TCTA2 = 0x2 - Configure as the input/output signal from CTIMER A2 GPIO20 = 0x3 - Configure as GPIO20 |
2 | PAD20STRNG | RW | Pad 20 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD20INPEN | RW | Pad 20 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD20PULL | RW | Pad 20 pulldown enable DIS = 0x0 - Pulldown disabled EN = 0x1 - Pulldown enabled |
Instance 0 Address: | 0x40010018 |
This register controls the pad configuration controls for PAD27 through PAD24. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD27FNCSEL
0x3 |
PAD27STRNG
0x0 |
PAD27INPEN
0x0 |
PAD27PULL
0x0 |
RSVD
0x0 |
PAD26FNCSEL
0x3 |
PAD26STRNG
0x0 |
PAD26INPEN
0x0 |
PAD26PULL
0x0 |
RSVD
0x0 |
PAD25FNCSEL
0x3 |
PAD25STRNG
0x0 |
PAD25INPEN
0x0 |
PAD25PULL
0x0 |
RSVD
0x0 |
PAD24FNCSEL
0x3 |
PAD24STRNG
0x0 |
PAD24INPEN
0x0 |
PAD24PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28:27 | PAD27FNCSEL | RW | Pad 27 function select EXTHF = 0x0 - Configure as the external HFRC clock signal M1nCE4 = 0x1 - Configure as the SPI channel 4 nCE signal from IOMSTR1 TCTA1 = 0x2 - Configure as the input/output signal from CTIMER A1 GPIO27 = 0x3 - Configure as GPIO27 |
26 | PAD27STRNG | RW | Pad 27 drive strentgh LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD27INPEN | RW | Pad 27 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD27PULL | RW | Pad 27 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:21 | RSVD | RO | RESERVED |
20:19 | PAD26FNCSEL | RW | Pad 26 function select EXTLF = 0x0 - Configure as the external LFRC clock signal M0nCE3 = 0x1 - Configure as the SPI channel 3 nCE signal from IOMSTR0 TCTB0 = 0x2 - Configure as the input/output signal from CTIMER B0 GPIO26 = 0x3 - Configure as GPIO26 |
18 | PAD26STRNG | RW | Pad 26 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD26INPEN | RW | Pad 26 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD26PULL | RW | Pad 26 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:13 | RSVD | RO | RESERVED |
12:11 | PAD25FNCSEL | RW | Pad 25 function select EXTXT = 0x0 - Configure as the external XT clock signal M0nCE2 = 0x1 - Configure as the SPI channel 2 nCE signal from IOMSTR0 TCTA0 = 0x2 - Configure as the input/output signal from CTIMER A0 GPIO25 = 0x3 - Configure as GPIO25 |
10 | PAD25STRNG | RW | Pad 25 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD25INPEN | RW | Pad 25 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD25PULL | RW | Pad 25 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:5 | RSVD | RO | RESERVED |
4:3 | PAD24FNCSEL | RW | Pad 24 function select DIS = 0x0 - Pad disabled M0nCE1 = 0x1 - Configure as the SPI channel 1 nCE signal from IOMSTR0 CLKOUT = 0x2 - Configure as the CLKOUT signal GPIO24 = 0x3 - Configure as GPIO24 |
2 | PAD24STRNG | RW | Pad 24 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD24INPEN | RW | Pad 24 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD24PULL | RW | Pad 24 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x4001001C |
This register controls the pad configuration controls for PAD31 through PAD28. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD31FNCSEL
0x3 |
PAD31STRNG
0x0 |
PAD31INPEN
0x0 |
PAD31PULL
0x0 |
RSVD
0x0 |
PAD30FNCSEL
0x3 |
PAD30STRNG
0x0 |
PAD30INPEN
0x0 |
PAD30PULL
0x0 |
RSVD
0x0 |
PAD29FNCSEL
0x3 |
PAD29STRNG
0x0 |
PAD29INPEN
0x0 |
PAD29PULL
0x0 |
RSVD
0x0 |
PAD28FNCSEL
0x3 |
PAD28STRNG
0x0 |
PAD28INPEN
0x0 |
PAD28PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28:27 | PAD31FNCSEL | RW | Pad 31 function select ADC6 = 0x0 - Configure as the analog ADC input 6 signal M0nCE4 = 0x1 - Configure as the SPI channel 4 nCE signal from IOMSTR0 TCTA3 = 0x2 - Configure as the input/output signal from CTIMER A3 GPIO31 = 0x3 - Configure as GPIO31 |
26 | PAD31STRNG | RW | Pad 31 drive strentgh LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD31INPEN | RW | Pad 31 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD31PULL | RW | Pad 31 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:21 | RSVD | RO | RESERVED |
20:19 | PAD30FNCSEL | RW | Pad 30 function select ADC5 = 0x0 - Configure as the analog ADC input 5 signal M1nCE7 = 0x1 - Configure as the SPI channel 7 nCE signal from IOMSTR1 TCTB2 = 0x2 - Configure as the input/output signal from CTIMER B2 GPIO30 = 0x3 - Configure as GPIO30 |
18 | PAD30STRNG | RW | Pad 30 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD30INPEN | RW | Pad 30 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD30PULL | RW | Pad 30 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:13 | RSVD | RO | RESERVED |
12:11 | PAD29FNCSEL | RW | Pad 29 function select ADC4 = 0x0 - Configure as the analog ADC input 4 signal M1nCE6 = 0x1 - Configure as the SPI channel 6 nCE signal from IOMSTR1 TCTA2 = 0x2 - Configure as the input/output signal from CTIMER A2 GPIO29 = 0x3 - Configure as GPIO29 |
10 | PAD29STRNG | RW | Pad 29 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD29INPEN | RW | Pad 29 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD29PULL | RW | Pad 29 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:5 | RSVD | RO | RESERVED |
4:3 | PAD28FNCSEL | RW | Pad 28 function select DIS = 0x0 - Pad disabled M1nCE5 = 0x1 - Configure as the SPI channel 5 nCE signal from IOMSTR1 TCTB1 = 0x2 - Configure as the input/output signal from CTIMER B1 GPIO28 = 0x3 - Configure as GPIO28 |
2 | PAD28STRNG | RW | Pad 28 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD28INPEN | RW | Pad 28 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD28PULL | RW | Pad 28 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x40010020 |
This register controls the pad configuration controls for PAD35 through PAD32. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD35FNCSEL
0x3 |
PAD35STRNG
0x0 |
PAD35INPEN
0x0 |
PAD35PULL
0x0 |
RSVD
0x0 |
PAD34FNCSEL
0x3 |
PAD34STRNG
0x0 |
PAD34INPEN
0x0 |
PAD34PULL
0x0 |
RSVD
0x0 |
PAD33FNCSEL
0x3 |
PAD33STRNG
0x0 |
PAD33INPEN
0x0 |
PAD33PULL
0x0 |
RSVD
0x0 |
PAD32FNCSEL
0x3 |
PAD32STRNG
0x0 |
PAD32INPEN
0x0 |
PAD32PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28:27 | PAD35FNCSEL | RW | Pad 35 function select DIS = 0x0 - Pad disabled M1nCE0 = 0x1 - Configure as the SPI channel 0 nCE signal from IOMSTR1 UARTTX = 0x2 - Configure as the UART TX signal GPIO35 = 0x3 - Configure as GPIO35 |
26 | PAD35STRNG | RW | Pad 35 drive strentgh LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD35INPEN | RW | Pad 35 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD35PULL | RW | Pad 35 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:21 | RSVD | RO | RESERVED |
20:19 | PAD34FNCSEL | RW | Pad 34 function select CMPRF2 = 0x0 - Configure as the analog comparator reference 2 signal M0nCE7 = 0x1 - Configure as the SPI channel 7 nCE signal from IOMSTR0 DIS = 0x2 - Pad disabled GPIO34 = 0x3 - Configure as GPIO34 |
18 | PAD34STRNG | RW | Pad 34 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD34INPEN | RW | Pad 34 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD34PULL | RW | Pad 34 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:13 | RSVD | RO | RESERVED |
12:11 | PAD33FNCSEL | RW | Pad 33 function select CMPRF1 = 0x0 - Configure as the analog comparator reference 1 signal M0nCE6 = 0x1 - Configure as the SPI channel 6 nCE signal from IOMSTR0 DIS = 0x2 - Pad disabled GPIO33 = 0x3 - Configure as GPIO33 |
10 | PAD33STRNG | RW | Pad 33 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD33INPEN | RW | Pad 33 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD33PULL | RW | Pad 33 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:5 | RSVD | RO | RESERVED |
4:3 | PAD32FNCSEL | RW | Pad 32 function select ADC7 = 0x0 - Configure as the analog ADC input 7 signal M0nCE5 = 0x1 - Configure as the SPI channel 5 nCE signal from IOMSTR0 TCTB3 = 0x2 - Configure as the input/output signal from CTIMER B3 GPIO32 = 0x3 - Configure as GPIO32 |
2 | PAD32STRNG | RW | Pad 32 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD32INPEN | RW | Pad 32 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD32PULL | RW | Pad 32 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x40010024 |
This register controls the pad configuration controls for PAD39 through PAD36. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD39FNCSEL
0x3 |
PAD39STRNG
0x0 |
PAD39INPEN
0x0 |
PAD39PULL
0x0 |
RSVD
0x0 |
PAD38FNCSEL
0x3 |
PAD38STRNG
0x0 |
PAD38INPEN
0x0 |
PAD38PULL
0x0 |
RSVD
0x0 |
PAD37FNCSEL
0x3 |
PAD37STRNG
0x0 |
PAD37INPEN
0x0 |
PAD37PULL
0x0 |
RSVD
0x0 |
PAD36FNCSEL
0x3 |
PAD36STRNG
0x0 |
PAD36INPEN
0x0 |
PAD36PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28:27 | PAD39FNCSEL | RW | Pad 39 function select TRIG2 = 0x0 - Configure as the ADC Trigger 2 signal UARTTX = 0x1 - Configure as the UART TX signal CLKOUT = 0x2 - Configure as the CLKOUT signal GPIO39 = 0x3 - Configure as GPIO39 |
26 | PAD39STRNG | RW | Pad 39 drive strentgh LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD39INPEN | RW | Pad 39 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD39PULL | RW | Pad 39 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:21 | RSVD | RO | RESERVED |
20:19 | PAD38FNCSEL | RW | Pad 38 function select TRIG1 = 0x0 - Configure as the ADC Trigger 1 signal M1nCE3 = 0x1 - Configure as the SPI channel 3 nCE signal from IOMSTR1 UACTS = 0x2 - Configure as the UART CTS signal GPIO38 = 0x3 - Configure as GPIO38 |
18 | PAD38STRNG | RW | Pad 38 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD38INPEN | RW | Pad 38 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD38PULL | RW | Pad 38 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:13 | RSVD | RO | RESERVED |
12:11 | PAD37FNCSEL | RW | Pad 37 function select TRIG0 = 0x0 - Configure as the ADC Trigger 0 signal M1nCE2 = 0x1 - Configure as the SPI channel 2 nCE signal from IOMSTR1 UARTS = 0x2 - Configure as the UART RTS signal GPIO37 = 0x3 - Configure as GPIO37 |
10 | PAD37STRNG | RW | Pad 37 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD37INPEN | RW | Pad 37 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD37PULL | RW | Pad 37 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:5 | RSVD | RO | RESERVED |
4:3 | PAD36FNCSEL | RW | Pad 36 function select DIS = 0x0 - Pad disabled M1nCE1 = 0x1 - Configure as the SPI channel 1 nCE signal from IOMSTR1 UARTRX = 0x2 - Configure as the UART RX signal GPIO36 = 0x3 - Configure as GPIO36 |
2 | PAD36STRNG | RW | Pad 36 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD36INPEN | RW | Pad 36 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD36PULL | RW | Pad 36 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x40010028 |
This register controls the pad configuration controls for PAD43 through PAD40. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD43FNCSEL
0x3 |
PAD43STRNG
0x0 |
PAD43INPEN
0x0 |
PAD43PULL
0x0 |
RSVD
0x0 |
PAD42FNCSEL
0x3 |
PAD42STRNG
0x0 |
PAD42INPEN
0x0 |
PAD42PULL
0x0 |
RSVD
0x0 |
PAD41FNCSEL
0x3 |
PAD41STRNG
0x0 |
PAD41INPEN
0x0 |
PAD41PULL
0x0 |
RSVD
0x0 |
PAD40FNCSEL
0x3 |
PAD40STRNG
0x0 |
PAD40INPEN
0x0 |
PAD40PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28:27 | PAD43FNCSEL | RW | Pad 43 function select TRIG6 = 0x0 - Configure as the ADC Trigger 6 signal M0nCE1 = 0x1 - Configure as the SPI channel 1 nCE signal from IOMSTR0 TCTB0 = 0x2 - Configure as the input/output signal from CTIMER B0 GPIO43 = 0x3 - Configure as GPIO43 |
26 | PAD43STRNG | RW | Pad 43 drive strentgh LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD43INPEN | RW | Pad 43 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD43PULL | RW | Pad 43 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:21 | RSVD | RO | RESERVED |
20:19 | PAD42FNCSEL | RW | Pad 42 function select TRIG5 = 0x0 - Configure as the ADC Trigger 5 signal M0nCE0 = 0x1 - Configure as the SPI channel 0 nCE signal from IOMSTR0 TCTA0 = 0x2 - Configure as the input/output signal from CTIMER A0 GPIO42 = 0x3 - Configure as GPIO42 |
18 | PAD42STRNG | RW | Pad 42 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD42INPEN | RW | Pad 42 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD42PULL | RW | Pad 42 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:13 | RSVD | RO | RESERVED |
12:11 | PAD41FNCSEL | RW | Pad 41 function select TRIG4 = 0x0 - Configure as the ADC Trigger 4 signal DIS = 0x1 - Pad disabled SWO = 0x2 - Configure as the serial wire debug SWO signal GPIO41 = 0x3 - Configure as GPIO41 |
10 | PAD41STRNG | RW | Pad 41 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD41INPEN | RW | Pad 41 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD41PULL | RW | Pad 41 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:5 | RSVD | RO | RESERVED |
4:3 | PAD40FNCSEL | RW | Pad 40 function select TRIG3 = 0x0 - Configure as the ADC Trigger 3 signal UARTRX = 0x1 - Configure as the UART RX signal DIS = 0x2 - Pad disabled GPIO40 = 0x3 - Configure as GPIO40 |
2 | PAD40STRNG | RW | Pad 40 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD40INPEN | RW | Pad 40 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD40PULL | RW | Pad 40 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x4001002C |
This register controls the pad configuration controls for PAD47 through PAD44. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD47FNCSEL
0x3 |
PAD47STRNG
0x0 |
PAD47INPEN
0x0 |
PAD47PULL
0x0 |
RSVD
0x0 |
PAD46FNCSEL
0x3 |
PAD46STRNG
0x0 |
PAD46INPEN
0x0 |
PAD46PULL
0x0 |
RSVD
0x0 |
PAD45FNCSEL
0x3 |
PAD45STRNG
0x0 |
PAD45INPEN
0x0 |
PAD45PULL
0x0 |
RSVD
0x0 |
PAD44FNCSEL
0x3 |
PAD44STRNG
0x0 |
PAD44INPEN
0x0 |
PAD44PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:29 | RSVD | RO | RESERVED |
28:27 | PAD47FNCSEL | RW | Pad 47 function select DIS = 0x0 - Pad disabled M0nCE5 = 0x1 - Configure as the SPI channel 5 nCE signal from IOMSTR0 TCTB2 = 0x2 - Configure as the input/output signal from CTIMER B2 GPIO47 = 0x3 - Configure as GPIO47 |
26 | PAD47STRNG | RW | Pad 47 drive strentgh LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
25 | PAD47INPEN | RW | Pad 47 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
24 | PAD47PULL | RW | Pad 47 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
23:21 | RSVD | RO | RESERVED |
20:19 | PAD46FNCSEL | RW | Pad 46 function select DIS = 0x0 - Pad disabled M0nCE4 = 0x1 - Configure as the SPI channel 4 nCE signal from IOMSTR0 TCTA2 = 0x2 - Configure as the input/output signal from CTIMER A2 GPIO46 = 0x3 - Configure as GPIO46 |
18 | PAD46STRNG | RW | Pad 46 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
17 | PAD46INPEN | RW | Pad 46 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
16 | PAD46PULL | RW | Pad 46 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
15:13 | RSVD | RO | RESERVED |
12:11 | PAD45FNCSEL | RW | Pad 45 function select DIS = 0x0 - Pad disabled M0nCE3 = 0x1 - Configure as the SPI channel 3 nCE signal from IOMSTR0 TCTB1 = 0x2 - Configure as the input/output signal from CTIMER B1 GPIO45 = 0x3 - Configure as GPIO45 |
10 | PAD45STRNG | RW | Pad 45 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD45INPEN | RW | Pad 45 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD45PULL | RW | Pad 45 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:5 | RSVD | RO | RESERVED |
4:3 | PAD44FNCSEL | RW | Pad 44 function select TRIG7 = 0x0 - Configure as the ADC Trigger 7 signal M0nCE2 = 0x1 - Configure as the SPI channel 2 nCE signal from IOMSTR0 TCTA1 = 0x2 - Configure as the input/output signal from CTIMER A1 GPIO44 = 0x3 - Configure as GPIO44 |
2 | PAD44STRNG | RW | Pad 44 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD44INPEN | RW | Pad 44 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD44PULL | RW | Pad 44 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x40010030 |
This register controls the pad configuration controls for PAD49 through PAD48. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PAD49FNCSEL
0x3 |
PAD49STRNG
0x0 |
PAD49INPEN
0x0 |
PAD49PULL
0x0 |
RSVD
0x0 |
PAD48FNCSEL
0x3 |
PAD48STRNG
0x0 |
PAD48INPEN
0x0 |
PAD48PULL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:13 | RSVD | RO | RESERVED |
12:11 | PAD49FNCSEL | RW | Pad 49 function select DIS = 0x0 - Pad disabled M0nCE7 = 0x1 - Configure as the SPI channel 7 nCE signal from IOMSTR0 TCTB3 = 0x2 - Configure as the input/output signal from CTIMER B3 GPIO49 = 0x3 - Configure as GPIO49 |
10 | PAD49STRNG | RW | Pad 49 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
9 | PAD49INPEN | RW | Pad 49 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
8 | PAD49PULL | RW | Pad 49 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
7:5 | RSVD | RO | RESERVED |
4:3 | PAD48FNCSEL | RW | Pad 48 function select DIS = 0x0 - Pad disabled M0nCE6 = 0x1 - Configure as the SPI channel 6 nCE signal from IOMSTR0 TCTA3 = 0x2 - Configure as the input/output signal from CTIMER A3 GPIO48 = 0x3 - Configure as GPIO48 |
2 | PAD48STRNG | RW | Pad 48 drive strength LOW = 0x0 - Low drive strength HIGH = 0x1 - High drive strength |
1 | PAD48INPEN | RW | Pad 48 input enable DIS = 0x0 - Pad input disabled EN = 0x1 - Pad input enabled |
0 | PAD48PULL | RW | Pad 48 pullup enable DIS = 0x0 - Pullup disabled EN = 0x1 - Pullup enabled |
Instance 0 Address: | 0x40010040 |
GPIO configuration controls for GPIO[7:0]. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO7INTD
0x0 |
GPIO7OUTCFG
0x0 |
GPIO7INCFG
0x0 |
GPIO6INTD
0x0 |
GPIO6OUTCFG
0x0 |
GPIO6INCFG
0x0 |
GPIO5INTD
0x0 |
GPIO5OUTCFG
0x0 |
GPIO5INCFG
0x0 |
GPIO4INTD
0x0 |
GPIO4OUTCFG
0x0 |
GPIO4INCFG
0x0 |
GPIO3INTD
0x0 |
GPIO3OUTCFG
0x0 |
GPIO3INCFG
0x0 |
GPIO2INTD
0x0 |
GPIO2OUTCFG
0x0 |
GPIO2INCFG
0x0 |
GPIO1INTD
0x0 |
GPIO1OUTCFG
0x0 |
GPIO1INCFG
0x0 |
GPIO0INTD
0x0 |
GPIO0OUTCFG
0x0 |
GPIO0INCFG
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO7INTD | RW | GPIO7 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
30:29 | GPIO7OUTCFG | RW | GPIO7 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
28 | GPIO7INCFG | RW | GPIO7 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
27 | GPIO6INTD | RW | GPIO6 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
26:25 | GPIO6OUTCFG | RW | GPIO6 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
24 | GPIO6INCFG | RW | GPIO6 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
23 | GPIO5INTD | RW | GPIO5 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
22:21 | GPIO5OUTCFG | RW | GPIO5 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
20 | GPIO5INCFG | RW | GPIO5 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
19 | GPIO4INTD | RW | GPIO4 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
18:17 | GPIO4OUTCFG | RW | GPIO4 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
16 | GPIO4INCFG | RW | GPIO4 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
15 | GPIO3INTD | RW | GPIO3 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
14:13 | GPIO3OUTCFG | RW | GPIO3 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
12 | GPIO3INCFG | RW | GPIO3 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
11 | GPIO2INTD | RW | GPIO2 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
10:9 | GPIO2OUTCFG | RW | GPIO2 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
8 | GPIO2INCFG | RW | GPIO2 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
7 | GPIO1INTD | RW | GPIO1 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
6:5 | GPIO1OUTCFG | RW | GPIO1 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
4 | GPIO1INCFG | RW | GPIO1 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
3 | GPIO0INTD | RW | GPIO0 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
2:1 | GPIO0OUTCFG | RW | GPIO0 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
0 | GPIO0INCFG | RW | GPIO0 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
Instance 0 Address: | 0x40010044 |
GPIO configuration controls for GPIO[15:8]. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO15INTD
0x0 |
GPIO15OUTCFG
0x0 |
GPIO15INCFG
0x0 |
GPIO14INTD
0x0 |
GPIO14OUTCFG
0x0 |
GPIO14INCFG
0x0 |
GPIO13INTD
0x0 |
GPIO13OUTCFG
0x0 |
GPIO13INCFG
0x0 |
GPIO12INTD
0x0 |
GPIO12OUTCFG
0x0 |
GPIO12INCFG
0x0 |
GPIO11INTD
0x0 |
GPIO11OUTCFG
0x0 |
GPIO11INCFG
0x0 |
GPIO10INTD
0x0 |
GPIO10OUTCFG
0x0 |
GPIO10INCFG
0x0 |
GPIO9INTD
0x0 |
GPIO9OUTCFG
0x0 |
GPIO9INCFG
0x0 |
GPIO8INTD
0x0 |
GPIO8OUTCFG
0x0 |
GPIO8INCFG
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO15INTD | RW | GPIO15 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
30:29 | GPIO15OUTCFG | RW | GPIO15 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
28 | GPIO15INCFG | RW | GPIO15 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
27 | GPIO14INTD | RW | GPIO14 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
26:25 | GPIO14OUTCFG | RW | GPIO14 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
24 | GPIO14INCFG | RW | GPIO14 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
23 | GPIO13INTD | RW | GPIO13 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
22:21 | GPIO13OUTCFG | RW | GPIO13 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
20 | GPIO13INCFG | RW | GPIO13 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
19 | GPIO12INTD | RW | GPIO12 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
18:17 | GPIO12OUTCFG | RW | GPIO12 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
16 | GPIO12INCFG | RW | GPIO12 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
15 | GPIO11INTD | RW | GPIO11 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
14:13 | GPIO11OUTCFG | RW | GPIO11 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
12 | GPIO11INCFG | RW | GPIO11 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
11 | GPIO10INTD | RW | GPIO10 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
10:9 | GPIO10OUTCFG | RW | GPIO10 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
8 | GPIO10INCFG | RW | GPIO10 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
7 | GPIO9INTD | RW | GPIO9 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
6:5 | GPIO9OUTCFG | RW | GPIO9 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
4 | GPIO9INCFG | RW | GPIO9 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
3 | GPIO8INTD | RW | GPIO8 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
2:1 | GPIO8OUTCFG | RW | GPIO8 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
0 | GPIO8INCFG | RW | GPIO8 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
Instance 0 Address: | 0x40010048 |
GPIO configuration controls for GPIO[23:16]. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO23INTD
0x0 |
GPIO23OUTCFG
0x0 |
GPIO23INCFG
0x0 |
GPIO22INTD
0x0 |
GPIO22OUTCFG
0x0 |
GPIO22INCFG
0x0 |
GPIO21INTD
0x0 |
GPIO21OUTCFG
0x0 |
GPIO21INCFG
0x1 |
GPIO20INTD
0x0 |
GPIO20OUTCFG
0x0 |
GPIO20INCFG
0x1 |
GPIO19INTD
0x0 |
GPIO19OUTCFG
0x0 |
GPIO19INCFG
0x0 |
GPIO18INTD
0x0 |
GPIO18OUTCFG
0x0 |
GPIO18INCFG
0x0 |
GPIO17INTD
0x0 |
GPIO17OUTCFG
0x0 |
GPIO17INCFG
0x0 |
GPIO16INTD
0x0 |
GPIO16OUTCFG
0x0 |
GPIO16INCFG
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO23INTD | RW | GPIO23 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
30:29 | GPIO23OUTCFG | RW | GPIO23 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
28 | GPIO23INCFG | RW | GPIO23 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
27 | GPIO22INTD | RW | GPIO22 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
26:25 | GPIO22OUTCFG | RW | GPIO22 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
24 | GPIO22INCFG | RW | GPIO22 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
23 | GPIO21INTD | RW | GPIO21 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
22:21 | GPIO21OUTCFG | RW | GPIO21 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
20 | GPIO21INCFG | RW | GPIO21 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
19 | GPIO20INTD | RW | GPIO20 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
18:17 | GPIO20OUTCFG | RW | GPIO20 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
16 | GPIO20INCFG | RW | GPIO20 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
15 | GPIO19INTD | RW | GPIO19 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
14:13 | GPIO19OUTCFG | RW | GPIO19 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
12 | GPIO19INCFG | RW | GPIO19 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
11 | GPIO18INTD | RW | GPIO18 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
10:9 | GPIO18OUTCFG | RW | GPIO18 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
8 | GPIO18INCFG | RW | GPIO18 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
7 | GPIO17INTD | RW | GPIO17 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
6:5 | GPIO17OUTCFG | RW | GPIO17 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
4 | GPIO17INCFG | RW | GPIO17 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
3 | GPIO16INTD | RW | GPIO16 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
2:1 | GPIO16OUTCFG | RW | GPIO16 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
0 | GPIO16INCFG | RW | GPIO16 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
Instance 0 Address: | 0x4001004C |
GPIO configuration controls for GPIO[31:24]. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO31INTD
0x0 |
GPIO31OUTCFG
0x0 |
GPIO31INCFG
0x0 |
GPIO30INTD
0x0 |
GPIO30OUTCFG
0x0 |
GPIO30INCFG
0x0 |
GPIO29INTD
0x0 |
GPIO29OUTCFG
0x0 |
GPIO29INCFG
0x0 |
GPIO28INTD
0x0 |
GPIO28OUTCFG
0x0 |
GPIO28INCFG
0x0 |
GPIO27INTD
0x0 |
GPIO27OUTCFG
0x0 |
GPIO27INCFG
0x0 |
GPIO26INTD
0x0 |
GPIO26OUTCFG
0x0 |
GPIO26INCFG
0x0 |
GPIO25INTD
0x0 |
GPIO25OUTCFG
0x0 |
GPIO25INCFG
0x0 |
GPIO24INTD
0x0 |
GPIO24OUTCFG
0x0 |
GPIO24INCFG
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO31INTD | RW | GPIO31 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
30:29 | GPIO31OUTCFG | RW | GPIO31 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
28 | GPIO31INCFG | RW | GPIO31 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
27 | GPIO30INTD | RW | GPIO30 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
26:25 | GPIO30OUTCFG | RW | GPIO30 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
24 | GPIO30INCFG | RW | GPIO30 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
23 | GPIO29INTD | RW | GPIO29 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
22:21 | GPIO29OUTCFG | RW | GPIO29 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
20 | GPIO29INCFG | RW | GPIO29 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
19 | GPIO28INTD | RW | GPIO28 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
18:17 | GPIO28OUTCFG | RW | GPIO28 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
16 | GPIO28INCFG | RW | GPIO28 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
15 | GPIO27INTD | RW | GPIO27 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
14:13 | GPIO27OUTCFG | RW | GPIO27 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
12 | GPIO27INCFG | RW | GPIO27 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
11 | GPIO26INTD | RW | GPIO26 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
10:9 | GPIO26OUTCFG | RW | GPIO26 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
8 | GPIO26INCFG | RW | GPIO26 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
7 | GPIO25INTD | RW | GPIO25 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
6:5 | GPIO25OUTCFG | RW | GPIO25 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
4 | GPIO25INCFG | RW | GPIO25 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
3 | GPIO24INTD | RW | GPIO24 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
2:1 | GPIO24OUTCFG | RW | GPIO24 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
0 | GPIO24INCFG | RW | GPIO24 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
Instance 0 Address: | 0x40010050 |
GPIO configuration controls for GPIO[39:32]. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO39INTD
0x0 |
GPIO39OUTCFG
0x0 |
GPIO39INCFG
0x0 |
GPIO38INTD
0x0 |
GPIO38OUTCFG
0x0 |
GPIO38INCFG
0x0 |
GPIO37INTD
0x0 |
GPIO37OUTCFG
0x0 |
GPIO37INCFG
0x0 |
GPIO36INTD
0x0 |
GPIO36OUTCFG
0x0 |
GPIO36INCFG
0x0 |
GPIO35INTD
0x0 |
GPIO35OUTCFG
0x0 |
GPIO35INCFG
0x0 |
GPIO34INTD
0x0 |
GPIO34OUTCFG
0x0 |
GPIO34INCFG
0x0 |
GPIO33INTD
0x0 |
GPIO33OUTCFG
0x0 |
GPIO33INCFG
0x0 |
GPIO32INTD
0x0 |
GPIO32OUTCFG
0x0 |
GPIO32INCFG
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO39INTD | RW | GPIO39 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
30:29 | GPIO39OUTCFG | RW | GPIO39 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
28 | GPIO39INCFG | RW | GPIO39 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
27 | GPIO38INTD | RW | GPIO38 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
26:25 | GPIO38OUTCFG | RW | GPIO38 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
24 | GPIO38INCFG | RW | GPIO38 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
23 | GPIO37INTD | RW | GPIO37 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
22:21 | GPIO37OUTCFG | RW | GPIO37 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
20 | GPIO37INCFG | RW | GPIO37 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
19 | GPIO36INTD | RW | GPIO36 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
18:17 | GPIO36OUTCFG | RW | GPIO36 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
16 | GPIO36INCFG | RW | GPIO36 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
15 | GPIO35INTD | RW | GPIO35 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
14:13 | GPIO35OUTCFG | RW | GPIO35 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
12 | GPIO35INCFG | RW | GPIO35 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
11 | GPIO34INTD | RW | GPIO34 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
10:9 | GPIO34OUTCFG | RW | GPIO34 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
8 | GPIO34INCFG | RW | GPIO34 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
7 | GPIO33INTD | RW | GPIO33 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
6:5 | GPIO33OUTCFG | RW | GPIO33 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
4 | GPIO33INCFG | RW | GPIO33 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
3 | GPIO32INTD | RW | GPIO32 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
2:1 | GPIO32OUTCFG | RW | GPIO32 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
0 | GPIO32INCFG | RW | GPIO32 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
Instance 0 Address: | 0x40010054 |
GPIO configuration controls for GPIO[47:40]. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO47INTD
0x0 |
GPIO47OUTCFG
0x0 |
GPIO47INCFG
0x0 |
GPIO46INTD
0x0 |
GPIO46OUTCFG
0x0 |
GPIO46INCFG
0x0 |
GPIO45INTD
0x0 |
GPIO45OUTCFG
0x0 |
GPIO45INCFG
0x0 |
GPIO44INTD
0x0 |
GPIO44OUTCFG
0x0 |
GPIO44INCFG
0x0 |
GPIO43INTD
0x0 |
GPIO43OUTCFG
0x0 |
GPIO43INCFG
0x0 |
GPIO42INTD
0x0 |
GPIO42OUTCFG
0x0 |
GPIO42INCFG
0x0 |
GPIO41INTD
0x0 |
GPIO41OUTCFG
0x0 |
GPIO41INCFG
0x0 |
GPIO40INTD
0x0 |
GPIO40OUTCFG
0x0 |
GPIO40INCFG
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO47INTD | RW | GPIO47 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
30:29 | GPIO47OUTCFG | RW | GPIO47 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
28 | GPIO47INCFG | RW | GPIO47 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
27 | GPIO46INTD | RW | GPIO46 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
26:25 | GPIO46OUTCFG | RW | GPIO46 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
24 | GPIO46INCFG | RW | GPIO46 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
23 | GPIO45INTD | RW | GPIO45 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
22:21 | GPIO45OUTCFG | RW | GPIO45 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
20 | GPIO45INCFG | RW | GPIO45 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
19 | GPIO44INTD | RW | GPIO44 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
18:17 | GPIO44OUTCFG | RW | GPIO44 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
16 | GPIO44INCFG | RW | GPIO44 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
15 | GPIO43INTD | RW | GPIO43 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
14:13 | GPIO43OUTCFG | RW | GPIO43 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
12 | GPIO43INCFG | RW | GPIO43 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
11 | GPIO42INTD | RW | GPIO42 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
10:9 | GPIO42OUTCFG | RW | GPIO42 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
8 | GPIO42INCFG | RW | GPIO42 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
7 | GPIO41INTD | RW | GPIO41 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
6:5 | GPIO41OUTCFG | RW | GPIO41 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
4 | GPIO41INCFG | RW | GPIO41 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
3 | GPIO40INTD | RW | GPIO40 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
2:1 | GPIO40OUTCFG | RW | GPIO40 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
0 | GPIO40INCFG | RW | GPIO40 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
Instance 0 Address: | 0x40010058 |
GPIO configuration controls for GPIO[49:48]. Writes to this register must be unlocked by the PADKEY register.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
GPIO49INTD
0x0 |
GPIO49OUTCFG
0x0 |
GPIO49INCFG
0x0 |
GPIO48INTD
0x0 |
GPIO48OUTCFG
0x0 |
GPIO48INCFG
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:8 | RSVD | RO | RESERVED |
7 | GPIO49INTD | RW | GPIO49 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
6:5 | GPIO49OUTCFG | RW | GPIO49 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
4 | GPIO49INCFG | RW | GPIO49 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
3 | GPIO48INTD | RW | GPIO48 interrupt direction. INTLH = 0x0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Interrupt on high to low GPIO transition |
2:1 | GPIO48OUTCFG | RW | GPIO48 output configuration. DIS = 0x0 - Output disabled PUSHPULL = 0x1 - Output is push-pull OD = 0x2 - Output is open drain TS = 0x3 - Output is tri-state |
0 | GPIO48INCFG | RW | GPIO48 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - Readback will always be zero |
Instance 0 Address: | 0x40010060 |
Key Register for all pad configuration registers
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PADKEY
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | PADKEY | RW | Key register value. Key = 0x73 - Key |
Instance 0 Address: | 0x40010080 |
GPIO Input Register A
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RDA
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | RDA | RO | GPIO31-0 read data. |
Instance 0 Address: | 0x40010084 |
GPIO Input Register B
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
RDB
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17:0 | RDB | RO | GPIO49-32 read data. |
Instance 0 Address: | 0x40010088 |
GPIO Output Register A
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WTA
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | WTA | RW | GPIO31-0 write data. |
Instance 0 Address: | 0x4001008C |
GPIO Output Register B
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
WTB
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17:0 | WTB | RW | GPIO49-32 write data. |
Instance 0 Address: | 0x40010090 |
GPIO Output Register A Set
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WTSA
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | WTSA | WO | Set the GPIO31-0 write data. |
Instance 0 Address: | 0x40010094 |
GPIO Output Register B Set
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
WTSB
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17:0 | WTSB | WO | Set the GPIO49-32 write data. |
Instance 0 Address: | 0x40010098 |
GPIO Output Register A Clear
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WTCA
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | WTCA | WO | Clear the GPIO31-0 write data. |
Instance 0 Address: | 0x4001009C |
GPIO Output Register B Clear
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
WTCB
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17:0 | WTCB | WO | Clear the GPIO49-32 write data. |
Instance 0 Address: | 0x400100A0 |
GPIO Enable Register A
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ENA
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | ENA | RW | GPIO31-0 output enables |
Instance 0 Address: | 0x400100A4 |
GPIO Enable Register B
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
ENB
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17:0 | ENB | RW | GPIO49-32 output enables |
Instance 0 Address: | 0x400100A8 |
GPIO Enable Register A Set
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ENSA
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | ENSA | RW | Set the GPIO31-0 output enables |
Instance 0 Address: | 0x400100AC |
GPIO Enable Register B Set
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
ENSB
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17:0 | ENSB | RW | Set the GPIO49-32 output enables |
Instance 0 Address: | 0x400100B4 |
GPIO Enable Register A Clear
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ENCA
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | ENCA | RW | Clear the GPIO31-0 output enables |
Instance 0 Address: | 0x400100B8 |
GPIO Enable Register B Clear
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
ENCB
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17:0 | ENCB | RW | Clear the GPIO49-32 output enables |
Instance 0 Address: | 0x40010200 |
Set bits in this register to allow this module to generate the corresponding interrupt.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO31
0x0 |
GPIO30
0x0 |
GPIO29
0x0 |
GPIO28
0x0 |
GPIO27
0x0 |
GPIO26
0x0 |
GPIO25
0x0 |
GPIO24
0x0 |
GPIO23
0x0 |
GPIO22
0x0 |
GPIO21
0x0 |
GPIO20
0x0 |
GPIO19
0x0 |
GPIO18
0x0 |
GPIO17
0x0 |
GPIO16
0x0 |
GPIO15
0x0 |
GPIO14
0x0 |
GPIO13
0x0 |
GPIO12
0x0 |
GPIO11
0x0 |
GPIO10
0x0 |
GPIO9
0x0 |
GPIO8
0x0 |
GPIO7
0x0 |
GPIO6
0x0 |
GPIO5
0x0 |
GPIO4
0x0 |
GPIO3
0x0 |
GPIO2
0x0 |
GPIO1
0x0 |
GPIO0
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO31 | RW | GPIO31 interrupt. |
30 | GPIO30 | RW | GPIO30 interrupt. |
29 | GPIO29 | RW | GPIO29 interrupt. |
28 | GPIO28 | RW | GPIO28 interrupt. |
27 | GPIO27 | RW | GPIO27 interrupt. |
26 | GPIO26 | RW | GPIO26 interrupt. |
25 | GPIO25 | RW | GPIO25 interrupt. |
24 | GPIO24 | RW | GPIO24 interrupt. |
23 | GPIO23 | RW | GPIO23 interrupt. |
22 | GPIO22 | RW | GPIO22 interrupt. |
21 | GPIO21 | RW | GPIO21 interrupt. |
20 | GPIO20 | RW | GPIO20 interrupt. |
19 | GPIO19 | RW | GPIO19 interrupt. |
18 | GPIO18 | RW | GPIO18interrupt. |
17 | GPIO17 | RW | GPIO17 interrupt. |
16 | GPIO16 | RW | GPIO16 interrupt. |
15 | GPIO15 | RW | GPIO15 interrupt. |
14 | GPIO14 | RW | GPIO14 interrupt. |
13 | GPIO13 | RW | GPIO13 interrupt. |
12 | GPIO12 | RW | GPIO12 interrupt. |
11 | GPIO11 | RW | GPIO11 interrupt. |
10 | GPIO10 | RW | GPIO10 interrupt. |
9 | GPIO9 | RW | GPIO9 interrupt. |
8 | GPIO8 | RW | GPIO8 interrupt. |
7 | GPIO7 | RW | GPIO7 interrupt. |
6 | GPIO6 | RW | GPIO6 interrupt. |
5 | GPIO5 | RW | GPIO5 interrupt. |
4 | GPIO4 | RW | GPIO4 interrupt. |
3 | GPIO3 | RW | GPIO3 interrupt. |
2 | GPIO2 | RW | GPIO2 interrupt. |
1 | GPIO1 | RW | GPIO1 interrupt. |
0 | GPIO0 | RW | GPIO0 interrupt. |
Instance 0 Address: | 0x40010204 |
Read bits from this register to discover the cause of a recent interrupt.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO31
0x0 |
GPIO30
0x0 |
GPIO29
0x0 |
GPIO28
0x0 |
GPIO27
0x0 |
GPIO26
0x0 |
GPIO25
0x0 |
GPIO24
0x0 |
GPIO23
0x0 |
GPIO22
0x0 |
GPIO21
0x0 |
GPIO20
0x0 |
GPIO19
0x0 |
GPIO18
0x0 |
GPIO17
0x0 |
GPIO16
0x0 |
GPIO15
0x0 |
GPIO14
0x0 |
GPIO13
0x0 |
GPIO12
0x0 |
GPIO11
0x0 |
GPIO10
0x0 |
GPIO9
0x0 |
GPIO8
0x0 |
GPIO7
0x0 |
GPIO6
0x0 |
GPIO5
0x0 |
GPIO4
0x0 |
GPIO3
0x0 |
GPIO2
0x0 |
GPIO1
0x0 |
GPIO0
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO31 | RW | GPIO31 interrupt. |
30 | GPIO30 | RW | GPIO30 interrupt. |
29 | GPIO29 | RW | GPIO29 interrupt. |
28 | GPIO28 | RW | GPIO28 interrupt. |
27 | GPIO27 | RW | GPIO27 interrupt. |
26 | GPIO26 | RW | GPIO26 interrupt. |
25 | GPIO25 | RW | GPIO25 interrupt. |
24 | GPIO24 | RW | GPIO24 interrupt. |
23 | GPIO23 | RW | GPIO23 interrupt. |
22 | GPIO22 | RW | GPIO22 interrupt. |
21 | GPIO21 | RW | GPIO21 interrupt. |
20 | GPIO20 | RW | GPIO20 interrupt. |
19 | GPIO19 | RW | GPIO19 interrupt. |
18 | GPIO18 | RW | GPIO18interrupt. |
17 | GPIO17 | RW | GPIO17 interrupt. |
16 | GPIO16 | RW | GPIO16 interrupt. |
15 | GPIO15 | RW | GPIO15 interrupt. |
14 | GPIO14 | RW | GPIO14 interrupt. |
13 | GPIO13 | RW | GPIO13 interrupt. |
12 | GPIO12 | RW | GPIO12 interrupt. |
11 | GPIO11 | RW | GPIO11 interrupt. |
10 | GPIO10 | RW | GPIO10 interrupt. |
9 | GPIO9 | RW | GPIO9 interrupt. |
8 | GPIO8 | RW | GPIO8 interrupt. |
7 | GPIO7 | RW | GPIO7 interrupt. |
6 | GPIO6 | RW | GPIO6 interrupt. |
5 | GPIO5 | RW | GPIO5 interrupt. |
4 | GPIO4 | RW | GPIO4 interrupt. |
3 | GPIO3 | RW | GPIO3 interrupt. |
2 | GPIO2 | RW | GPIO2 interrupt. |
1 | GPIO1 | RW | GPIO1 interrupt. |
0 | GPIO0 | RW | GPIO0 interrupt. |
Instance 0 Address: | 0x40010208 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO31
0x0 |
GPIO30
0x0 |
GPIO29
0x0 |
GPIO28
0x0 |
GPIO27
0x0 |
GPIO26
0x0 |
GPIO25
0x0 |
GPIO24
0x0 |
GPIO23
0x0 |
GPIO22
0x0 |
GPIO21
0x0 |
GPIO20
0x0 |
GPIO19
0x0 |
GPIO18
0x0 |
GPIO17
0x0 |
GPIO16
0x0 |
GPIO15
0x0 |
GPIO14
0x0 |
GPIO13
0x0 |
GPIO12
0x0 |
GPIO11
0x0 |
GPIO10
0x0 |
GPIO9
0x0 |
GPIO8
0x0 |
GPIO7
0x0 |
GPIO6
0x0 |
GPIO5
0x0 |
GPIO4
0x0 |
GPIO3
0x0 |
GPIO2
0x0 |
GPIO1
0x0 |
GPIO0
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO31 | RW | GPIO31 interrupt. |
30 | GPIO30 | RW | GPIO30 interrupt. |
29 | GPIO29 | RW | GPIO29 interrupt. |
28 | GPIO28 | RW | GPIO28 interrupt. |
27 | GPIO27 | RW | GPIO27 interrupt. |
26 | GPIO26 | RW | GPIO26 interrupt. |
25 | GPIO25 | RW | GPIO25 interrupt. |
24 | GPIO24 | RW | GPIO24 interrupt. |
23 | GPIO23 | RW | GPIO23 interrupt. |
22 | GPIO22 | RW | GPIO22 interrupt. |
21 | GPIO21 | RW | GPIO21 interrupt. |
20 | GPIO20 | RW | GPIO20 interrupt. |
19 | GPIO19 | RW | GPIO19 interrupt. |
18 | GPIO18 | RW | GPIO18interrupt. |
17 | GPIO17 | RW | GPIO17 interrupt. |
16 | GPIO16 | RW | GPIO16 interrupt. |
15 | GPIO15 | RW | GPIO15 interrupt. |
14 | GPIO14 | RW | GPIO14 interrupt. |
13 | GPIO13 | RW | GPIO13 interrupt. |
12 | GPIO12 | RW | GPIO12 interrupt. |
11 | GPIO11 | RW | GPIO11 interrupt. |
10 | GPIO10 | RW | GPIO10 interrupt. |
9 | GPIO9 | RW | GPIO9 interrupt. |
8 | GPIO8 | RW | GPIO8 interrupt. |
7 | GPIO7 | RW | GPIO7 interrupt. |
6 | GPIO6 | RW | GPIO6 interrupt. |
5 | GPIO5 | RW | GPIO5 interrupt. |
4 | GPIO4 | RW | GPIO4 interrupt. |
3 | GPIO3 | RW | GPIO3 interrupt. |
2 | GPIO2 | RW | GPIO2 interrupt. |
1 | GPIO1 | RW | GPIO1 interrupt. |
0 | GPIO0 | RW | GPIO0 interrupt. |
Instance 0 Address: | 0x4001020C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPIO31
0x0 |
GPIO30
0x0 |
GPIO29
0x0 |
GPIO28
0x0 |
GPIO27
0x0 |
GPIO26
0x0 |
GPIO25
0x0 |
GPIO24
0x0 |
GPIO23
0x0 |
GPIO22
0x0 |
GPIO21
0x0 |
GPIO20
0x0 |
GPIO19
0x0 |
GPIO18
0x0 |
GPIO17
0x0 |
GPIO16
0x0 |
GPIO15
0x0 |
GPIO14
0x0 |
GPIO13
0x0 |
GPIO12
0x0 |
GPIO11
0x0 |
GPIO10
0x0 |
GPIO9
0x0 |
GPIO8
0x0 |
GPIO7
0x0 |
GPIO6
0x0 |
GPIO5
0x0 |
GPIO4
0x0 |
GPIO3
0x0 |
GPIO2
0x0 |
GPIO1
0x0 |
GPIO0
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | GPIO31 | RW | GPIO31 interrupt. |
30 | GPIO30 | RW | GPIO30 interrupt. |
29 | GPIO29 | RW | GPIO29 interrupt. |
28 | GPIO28 | RW | GPIO28 interrupt. |
27 | GPIO27 | RW | GPIO27 interrupt. |
26 | GPIO26 | RW | GPIO26 interrupt. |
25 | GPIO25 | RW | GPIO25 interrupt. |
24 | GPIO24 | RW | GPIO24 interrupt. |
23 | GPIO23 | RW | GPIO23 interrupt. |
22 | GPIO22 | RW | GPIO22 interrupt. |
21 | GPIO21 | RW | GPIO21 interrupt. |
20 | GPIO20 | RW | GPIO20 interrupt. |
19 | GPIO19 | RW | GPIO19 interrupt. |
18 | GPIO18 | RW | GPIO18interrupt. |
17 | GPIO17 | RW | GPIO17 interrupt. |
16 | GPIO16 | RW | GPIO16 interrupt. |
15 | GPIO15 | RW | GPIO15 interrupt. |
14 | GPIO14 | RW | GPIO14 interrupt. |
13 | GPIO13 | RW | GPIO13 interrupt. |
12 | GPIO12 | RW | GPIO12 interrupt. |
11 | GPIO11 | RW | GPIO11 interrupt. |
10 | GPIO10 | RW | GPIO10 interrupt. |
9 | GPIO9 | RW | GPIO9 interrupt. |
8 | GPIO8 | RW | GPIO8 interrupt. |
7 | GPIO7 | RW | GPIO7 interrupt. |
6 | GPIO6 | RW | GPIO6 interrupt. |
5 | GPIO5 | RW | GPIO5 interrupt. |
4 | GPIO4 | RW | GPIO4 interrupt. |
3 | GPIO3 | RW | GPIO3 interrupt. |
2 | GPIO2 | RW | GPIO2 interrupt. |
1 | GPIO1 | RW | GPIO1 interrupt. |
0 | GPIO0 | RW | GPIO0 interrupt. |
Instance 0 Address: | 0x40010210 |
Set bits in this register to allow this module to generate the corresponding interrupt.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
GPIO49
0x0 |
GPIO48
0x0 |
GPIO47
0x0 |
GPIO46
0x0 |
GPIO45
0x0 |
GPIO44
0x0 |
GPIO43
0x0 |
GPIO42
0x0 |
GPIO41
0x0 |
GPIO40
0x0 |
GPIO39
0x0 |
GPIO38
0x0 |
GPIO37
0x0 |
GPIO36
0x0 |
GPIO35
0x0 |
GPIO34
0x0 |
GPIO33
0x0 |
GPIO32
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17 | GPIO49 | RW | GPIO49 interrupt. |
16 | GPIO48 | RW | GPIO48 interrupt. |
15 | GPIO47 | RW | GPIO47 interrupt. |
14 | GPIO46 | RW | GPIO46 interrupt. |
13 | GPIO45 | RW | GPIO45 interrupt. |
12 | GPIO44 | RW | GPIO44 interrupt. |
11 | GPIO43 | RW | GPIO43 interrupt. |
10 | GPIO42 | RW | GPIO42 interrupt. |
9 | GPIO41 | RW | GPIO41 interrupt. |
8 | GPIO40 | RW | GPIO40 interrupt. |
7 | GPIO39 | RW | GPIO39 interrupt. |
6 | GPIO38 | RW | GPIO38 interrupt. |
5 | GPIO37 | RW | GPIO37 interrupt. |
4 | GPIO36 | RW | GPIO36 interrupt. |
3 | GPIO35 | RW | GPIO35 interrupt. |
2 | GPIO34 | RW | GPIO34 interrupt. |
1 | GPIO33 | RW | GPIO33 interrupt. |
0 | GPIO32 | RW | GPIO32 interrupt. |
Instance 0 Address: | 0x40010214 |
Read bits from this register to discover the cause of a recent interrupt.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
GPIO49
0x0 |
GPIO48
0x0 |
GPIO47
0x0 |
GPIO46
0x0 |
GPIO45
0x0 |
GPIO44
0x0 |
GPIO43
0x0 |
GPIO42
0x0 |
GPIO41
0x0 |
GPIO40
0x0 |
GPIO39
0x0 |
GPIO38
0x0 |
GPIO37
0x0 |
GPIO36
0x0 |
GPIO35
0x0 |
GPIO34
0x0 |
GPIO33
0x0 |
GPIO32
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17 | GPIO49 | RW | GPIO49 interrupt. |
16 | GPIO48 | RW | GPIO48 interrupt. |
15 | GPIO47 | RW | GPIO47 interrupt. |
14 | GPIO46 | RW | GPIO46 interrupt. |
13 | GPIO45 | RW | GPIO45 interrupt. |
12 | GPIO44 | RW | GPIO44 interrupt. |
11 | GPIO43 | RW | GPIO43 interrupt. |
10 | GPIO42 | RW | GPIO42 interrupt. |
9 | GPIO41 | RW | GPIO41 interrupt. |
8 | GPIO40 | RW | GPIO40 interrupt. |
7 | GPIO39 | RW | GPIO39 interrupt. |
6 | GPIO38 | RW | GPIO38 interrupt. |
5 | GPIO37 | RW | GPIO37 interrupt. |
4 | GPIO36 | RW | GPIO36 interrupt. |
3 | GPIO35 | RW | GPIO35 interrupt. |
2 | GPIO34 | RW | GPIO34 interrupt. |
1 | GPIO33 | RW | GPIO33 interrupt. |
0 | GPIO32 | RW | GPIO32 interrupt. |
Instance 0 Address: | 0x40010218 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
GPIO49
0x0 |
GPIO48
0x0 |
GPIO47
0x0 |
GPIO46
0x0 |
GPIO45
0x0 |
GPIO44
0x0 |
GPIO43
0x0 |
GPIO42
0x0 |
GPIO41
0x0 |
GPIO40
0x0 |
GPIO39
0x0 |
GPIO38
0x0 |
GPIO37
0x0 |
GPIO36
0x0 |
GPIO35
0x0 |
GPIO34
0x0 |
GPIO33
0x0 |
GPIO32
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17 | GPIO49 | RW | GPIO49 interrupt. |
16 | GPIO48 | RW | GPIO48 interrupt. |
15 | GPIO47 | RW | GPIO47 interrupt. |
14 | GPIO46 | RW | GPIO46 interrupt. |
13 | GPIO45 | RW | GPIO45 interrupt. |
12 | GPIO44 | RW | GPIO44 interrupt. |
11 | GPIO43 | RW | GPIO43 interrupt. |
10 | GPIO42 | RW | GPIO42 interrupt. |
9 | GPIO41 | RW | GPIO41 interrupt. |
8 | GPIO40 | RW | GPIO40 interrupt. |
7 | GPIO39 | RW | GPIO39 interrupt. |
6 | GPIO38 | RW | GPIO38 interrupt. |
5 | GPIO37 | RW | GPIO37 interrupt. |
4 | GPIO36 | RW | GPIO36 interrupt. |
3 | GPIO35 | RW | GPIO35 interrupt. |
2 | GPIO34 | RW | GPIO34 interrupt. |
1 | GPIO33 | RW | GPIO33 interrupt. |
0 | GPIO32 | RW | GPIO32 interrupt. |
Instance 0 Address: | 0x4001021C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
GPIO49
0x0 |
GPIO48
0x0 |
GPIO47
0x0 |
GPIO46
0x0 |
GPIO45
0x0 |
GPIO44
0x0 |
GPIO43
0x0 |
GPIO42
0x0 |
GPIO41
0x0 |
GPIO40
0x0 |
GPIO39
0x0 |
GPIO38
0x0 |
GPIO37
0x0 |
GPIO36
0x0 |
GPIO35
0x0 |
GPIO34
0x0 |
GPIO33
0x0 |
GPIO32
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:18 | RSVD | RO | RESERVED |
17 | GPIO49 | RW | GPIO49 interrupt. |
16 | GPIO48 | RW | GPIO48 interrupt. |
15 | GPIO47 | RW | GPIO47 interrupt. |
14 | GPIO46 | RW | GPIO46 interrupt. |
13 | GPIO45 | RW | GPIO45 interrupt. |
12 | GPIO44 | RW | GPIO44 interrupt. |
11 | GPIO43 | RW | GPIO43 interrupt. |
10 | GPIO42 | RW | GPIO42 interrupt. |
9 | GPIO41 | RW | GPIO41 interrupt. |
8 | GPIO40 | RW | GPIO40 interrupt. |
7 | GPIO39 | RW | GPIO39 interrupt. |
6 | GPIO38 | RW | GPIO38 interrupt. |
5 | GPIO37 | RW | GPIO37 interrupt. |
4 | GPIO36 | RW | GPIO36 interrupt. |
3 | GPIO35 | RW | GPIO35 interrupt. |
2 | GPIO34 | RW | GPIO34 interrupt. |
1 | GPIO33 | RW | GPIO33 interrupt. |
0 | GPIO32 | RW | GPIO32 interrupt. |