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Apollo Register Documentation v2.4.2
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0x00000000: | CACHECFG - Flash Cache Control Register |
0x00000004: | FLASHCFG - Flash Control Register |
0x00000008: | CTRL - Cache Control |
0x00000010: | NCR0START - Flash Cache Noncachable Region 0 Start |
0x00000014: | NCR0END - Flash Cache Noncachable Region 0 End |
0x00000018: | NCR1START - Flash Cache Noncachable Region 1 Start |
0x0000001C: | NCR1END - Flash Cache Noncachable Region 1 End |
0x00000040: | DMON0 - Data Cache Total Accesses |
0x00000044: | DMON1 - Data Cache Tag Lookups |
0x00000048: | DMON2 - Data Cache Hits |
0x0000004C: | DMON3 - Data Cache Line Hits |
0x00000050: | IMON0 - Instruction Cache Total Accesses |
0x00000054: | IMON1 - Instruction Cache Tag Lookups |
0x00000058: | IMON2 - Instruction Cache Hits |
0x0000005C: | IMON3 - Instruction Cache Line Hits |
Instance 0 Address: | 0x40018000 |
Flash Cache Control Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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RSVD
0x0 |
ENABLE_MONITOR
0x0 |
RSVD
0x0 |
DATA_CLKGATE
0x1 |
RSVD
0x0 |
CACHE_LS
0x1 |
CACHE_CLKGATE
0x1 |
DCACHE_ENABLE
0x0 |
ICACHE_ENABLE
0x0 |
CONFIG
0x5 |
ENABLE_NC1
0x0 |
ENABLE_NC0
0x0 |
LRU
0x0 |
ENABLE
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:25 | RSVD | RO | This bitfield is reserved for future use. |
24 | ENABLE_MONITOR | RW | Enable Cache Monitoring Stats. Cache monitoring consumes additional power and should only be enabled when profiling code and counters will increment when this bit is set. Counter values will be retained when this is set to 0, allowing software to enable/disable counting for multiple code segments. |
23:21 | RSVD | RO | This bitfield is reserved for future use. |
20 | DATA_CLKGATE | RW | Enable aggressive clock gating of entire data array. This bit should be set to 1 for optimal power efficiency. |
19:12 | RSVD | RO | This bitfield is reserved for future use. |
11 | CACHE_LS | RW | Enable LS (light sleep) of cache RAMs. Software should DISABLE this bit since cache activity is too high to benefit from LS usage. |
10 | CACHE_CLKGATE | RW | Enable clock gating of cache TAG RAM. Software should enable this bit for optimal power efficiency. |
9 | DCACHE_ENABLE | RW | Enable Flash Data Caching. |
8 | ICACHE_ENABLE | RW | Enable Flash Instruction Caching |
7:4 | CONFIG | RW | Sets the cache configuration W1_128B_512E = 0x4 - Direct mapped, 128-bit linesize, 512 entries (4 SRAMs active) W2_128B_512E = 0x5 - Two-way set associative, 128-bit linesize, 512 entries (8 SRAMs active) W1_128B_1024E = 0x8 - Direct mapped, 128-bit linesize, 1024 entries (8 SRAMs active) |
3 | ENABLE_NC1 | RW | Enable Non-cacheable region 1. See NCR1 registers to define the region. |
2 | ENABLE_NC0 | RW | Enable Non-cacheable region 0. See NCR0 registers to define the region. |
1 | LRU | RW | Sets the cache repleacment policy. 0=LRR (least recently replaced), 1=LRU (least recently used). LRR minimizes writes to the TAG SRAM. |
0 | ENABLE | RW | Enables the flash cache controller and enables power to the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE should be set to enable caching for each type of access. |
Instance 0 Address: | 0x40018004 |
Flash Control Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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RSVD
0x0 |
LPMMODE
0x0 |
LPM_RD_WAIT
0x8 |
RSVD
0x0 |
SEDELAY
0x7 |
RD_WAIT
0x3 |
Bits | Name | RW | Description |
---|---|---|---|
31:14 | RSVD | RO | This bitfield is reserved for future use. |
13:12 | LPMMODE | RW | Controls flash low power modes (control of LPM pin). NEVER = 0x0 - High power mode (LPM not used). STANDBY = 0x1 - Fast Standby mode. LPM deasserted for read operations, but asserted while flash IDLE. ALWAYS = 0x2 - Low Power mode. LPM always asserted for reads. LPM_RD_WAIT must be programmed to accomodate longer read access times. |
11:8 | LPM_RD_WAIT | RW | Sets flash waitstates when in LPM Mode 2 (RD_WAIT in LPM mode 2 only) |
7 | RSVD | RO | This bitfield is reserved for future use. |
6:4 | SEDELAY | RW | Sets SE delay (flash address setup). A value of 5 is recommended. |
3:0 | RD_WAIT | RW | Sets read waitstates for normal (fast) operation. A value of 1 is recommended. |
Instance 0 Address: | 0x40018008 |
Cache Control
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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RSVD
0x0 |
FLASH1_SLM_ENABLE
0x0 |
FLASH1_SLM_DISABLE
0x0 |
FLASH1_SLM_STATUS
0x0 |
RSVD
0x0 |
FLASH0_SLM_ENABLE
0x0 |
FLASH0_SLM_DISABLE
0x0 |
FLASH0_SLM_STATUS
0x0 |
RSVD
0x0 |
CACHE_READY
0x0 |
RESET_STAT
0x0 |
INVALIDATE
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:11 | RSVD | RO | This bitfield is reserved for future use. |
10 | FLASH1_SLM_ENABLE | WO | Enable Flash Sleep Mode. Write to 1 to put flash 1 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned. |
9 | FLASH1_SLM_DISABLE | WO | Disable Flash Sleep Mode. Write 1 to wake flash1 from sleep mode (reading the array will also automatically wake it). |
8 | FLASH1_SLM_STATUS | RO | Flash Sleep Mode Status. 1 indicates that flash1 is in sleep mode, 0 indicates flash1 is in normal mode. |
7 | RSVD | RO | This bitfield is reserved for future use. |
6 | FLASH0_SLM_ENABLE | WO | Enable Flash Sleep Mode. Write to 1 to put flash 0 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned. |
5 | FLASH0_SLM_DISABLE | WO | Disable Flash Sleep Mode. Write 1 to wake flash0 from sleep mode (reading the array will also automatically wake it). |
4 | FLASH0_SLM_STATUS | RO | Flash Sleep Mode Status. 1 indicates that flash0 is in sleep mode, 0 indicates flash0 is in normal mode. |
3 | RSVD | RO | This bitfield is reserved for future use. |
2 | CACHE_READY | RO | Cache Ready Status (enabled and not processing an invalidate operation) |
1 | RESET_STAT | WO | Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set. CLEAR = 0x1 - Clear Cache Stats |
0 | INVALIDATE | WO | Writing a 1 to this bitfield invalidates the flash cache contents. |
Instance 0 Address: | 0x40018010 |
Flash Cache Noncachable Region 0 Start
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
ADDR
0x0 |
RSVD
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:27 | RSVD | RO | This bitfield is reserved for future use. |
26:4 | ADDR | RW | Start address for non-cacheable region 0 |
3:0 | RSVD | RO | This bitfield is reserved for future use. |
Instance 0 Address: | 0x40018014 |
Flash Cache Noncachable Region 0 End
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
ADDR
0x0 |
RSVD
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:27 | RSVD | RO | This bitfield is reserved for future use. |
26:4 | ADDR | RW | End address for non-cacheable region 0 |
3:0 | RSVD | RO | This bitfield is reserved for future use. |
Instance 0 Address: | 0x40018018 |
Flash Cache Noncachable Region 1 Start
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
ADDR
0x0 |
RSVD
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:27 | RSVD | RO | This bitfield is reserved for future use. |
26:4 | ADDR | RW | Start address for non-cacheable region 1 |
3:0 | RSVD | RO | This bitfield is reserved for future use. |
Instance 0 Address: | 0x4001801C |
Flash Cache Noncachable Region 1 End
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
ADDR
0x0 |
RSVD
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:27 | RSVD | RO | This bitfield is reserved for future use. |
26:4 | ADDR | RW | End address for non-cacheable region 1 |
3:0 | RSVD | RO | This bitfield is reserved for future use. |
Instance 0 Address: | 0x40018040 |
Data Cache Total Accesses
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DACCESS_COUNT
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | DACCESS_COUNT | RO | Total accesses to data cache. All performance metrics should be relative to the number of accesses performed. |
Instance 0 Address: | 0x40018044 |
Data Cache Tag Lookups
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DLOOKUP_COUNT
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | DLOOKUP_COUNT | RO | Total tag lookups from data cache. |
Instance 0 Address: | 0x40018048 |
Data Cache Hits
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DHIT_COUNT
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | DHIT_COUNT | RO | Cache hits from lookup operations. |
Instance 0 Address: | 0x4001804C |
Data Cache Line Hits
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DLINE_COUNT
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | DLINE_COUNT | RO | Cache hits from line cache |
Instance 0 Address: | 0x40018050 |
Instruction Cache Total Accesses
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IACCESS_COUNT
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | IACCESS_COUNT | RO | Total accesses to Instruction cache |
Instance 0 Address: | 0x40018054 |
Instruction Cache Tag Lookups
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ILOOKUP_COUNT
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | ILOOKUP_COUNT | RO | Total tag lookups from Instruction cache |
Instance 0 Address: | 0x40018058 |
Instruction Cache Hits
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IHIT_COUNT
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | IHIT_COUNT | RO | Cache hits from lookup operations |
Instance 0 Address: | 0x4001805C |
Instruction Cache Line Hits
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ILINE_COUNT
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | ILINE_COUNT | RO | Cache hits from line cache |